mac/sram: simplify counter (use NextValue in FSM)
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@ -50,15 +50,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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"default" : inc.eq(4)
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})
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counter = Signal(lengthbits)
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counter_reset = Signal()
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counter_ce = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + inc)
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)
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counter = Signal(lengthbits)
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# Slot computation
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slot = Signal(slotbits)
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@ -79,7 +71,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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If(sink.valid,
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If(fifo.sink.ready,
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ongoing.eq(1),
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counter_ce.eq(1),
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NextValue(counter, counter + inc),
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NextState("WRITE")
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).Else(
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NextValue(self.errors.status, self.errors.status + 1),
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@ -92,7 +84,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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If(counter == eth_mtu,
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NextState("DISCARD_REMAINING")
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).Else(
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counter_ce.eq(1),
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NextValue(counter, counter + inc),
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ongoing.eq(1)
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),
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If(sink.last,
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@ -105,7 +97,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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)
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)
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fsm.act("DISCARD",
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counter_reset.eq(1),
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NextValue(counter, 0),
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NextState("IDLE")
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)
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fsm.act("DISCARD_REMAINING",
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@ -118,7 +110,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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fifo.sink.length.eq(counter)
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]
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fsm.act("TERMINATE",
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counter_reset.eq(1),
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NextValue(counter, 0),
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slot_ce.eq(1),
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fifo.sink.valid.eq(1),
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NextState("IDLE")
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@ -184,16 +176,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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]
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# Length computation
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counter = Signal(lengthbits)
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counter_reset = Signal()
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counter_ce = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + 4)
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)
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counter = Signal(lengthbits)
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# FSM
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last = Signal()
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@ -203,7 +186,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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self.submodules += fsm
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fsm.act("IDLE",
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counter_reset.eq(1),
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NextValue(counter, 0),
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If(fifo.source.valid,
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NextState("CHECK")
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)
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@ -238,7 +221,9 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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source.valid.eq(1),
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source.last.eq(last),
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If(source.ready,
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counter_ce.eq(~last),
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If(~last,
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NextValue(counter, counter + 4)
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),
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NextState("CHECK")
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)
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)
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