Hardware/liteeth
1
0
Fork 0
mirror of https://github.com/enjoy-digital/liteeth.git synced 2025-01-03 03:43:37 -05:00
Code Issues Projects Releases Packages Wiki Activity

Merge pull request #100 from fjullien/fix_trionrgmii

Browse source 
phy: trionrgmii: add 'properties' to GPIO
This commit is contained in:
enjoy-digital 2022-01-13 14:31:39 +01:00 committed by GitHub
commit c3e3dee0e9
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 22 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

38
liteeth/phy/trionrgmii.py
View file

@ -27,9 +27,10 @@ class LiteEthPHYRGMIITX(Module):
tx_data_h = []
tx_data_l = []
for n in range(4):
name = platform.get_pin_name(pads.tx_data[n])
pad = platform.get_pin_location(pads.tx_data[n])
name = f"auto_{name}"
name = platform.get_pin_name(pads.tx_data[n])
pad = platform.get_pin_location(pads.tx_data[n])
io_prop = platform.get_pin_properties(pads.tx_data[n])
name = f"auto_{name}"
tx_data_h.append(platform.add_iface_io(name + "_HI"))
tx_data_l.append(platform.add_iface_io(name + "_LO"))
@ -39,6 +40,7 @@ class LiteEthPHYRGMIITX(Module):
"mode" : "OUTPUT",
"name" : name,
"location" : pad,
"properties" : io_prop,
"size" : 1,
"out_reg" : "DDIO_RESYNC",
"out_clk_pin" : "auto_eth_tx_clk",
@ -71,9 +73,10 @@ class LiteEthPHYRGMIIRX(Module):
rx_data_h = []
rx_data_l = []
for n in range(4):
name = platform.get_pin_name(pads.rx_data[n])
pad = platform.get_pin_location(pads.rx_data[n])
name = f"auto_{name}"
name = platform.get_pin_name(pads.rx_data[n])
pad = platform.get_pin_location(pads.rx_data[n])
io_prop = platform.get_pin_properties(pads.rx_data[n])
name = f"auto_{name}"
rx_data_h.append(platform.add_iface_io(name + "_HI"))
rx_data_l.append(platform.add_iface_io(name + "_LO"))
@ -83,6 +86,7 @@ class LiteEthPHYRGMIIRX(Module):
"mode" : "INPUT",
"name" : name,
"location" : pad,
"properties" : io_prop,
"size" : 1,
"in_reg" : "DDIO_RESYNC",
"in_clk_pin" : "auto_eth_rx_clk",
@ -124,11 +128,12 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# -------
eth_rx_clk = platform.add_iface_io("auto_eth_rx_clk")
block = {
"type" : "GPIO",
"size" : 1,
"location" : platform.get_pin_location(clock_pads.rx)[0],
"name" : platform.get_pin_name(eth_rx_clk),
"mode" : "INPUT_CLK"
"type" : "GPIO",
"size" : 1,
"location" : platform.get_pin_location(clock_pads.rx)[0],
"properties" : platform.get_pin_properties(clock_pads.rx),
"name" : platform.get_pin_name(eth_rx_clk),
"mode" : "INPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)
self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
@ -139,11 +144,12 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# TX Clk.
# -------
block = {
"type" : "GPIO",
"size" : 1,
"location" : platform.get_pin_location(clock_pads.tx)[0],
"name" : "auto_eth_tx_clk_delayed",
"mode" : "OUTPUT_CLK"
"type" : "GPIO",
"size" : 1,
"location" : platform.get_pin_location(clock_pads.tx)[0],
"properties" : platform.get_pin_properties(clock_pads.tx),
"name" : "auto_eth_tx_clk_delayed",
"mode" : "OUTPUT_CLK"
}
platform.toolchain.ifacewriter.blocks.append(block)