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Merge pull request #100 from fjullien/fix_trionrgmii

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phy: trionrgmii: add 'properties' to GPIO
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enjoy-digital 2022-01-13 14:31:39 +01:00 committed by GitHub
commit c3e3dee0e9
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1 changed files with 22 additions and 16 deletions
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38
liteeth/phy/trionrgmii.py
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@ -27,9 +27,10 @@ class LiteEthPHYRGMIITX(Module):
tx_data_h = [] tx_data_h = []
tx_data_l = [] tx_data_l = []
for n in range(4): for n in range(4):
name = platform.get_pin_name(pads.tx_data[n]) name = platform.get_pin_name(pads.tx_data[n])
pad = platform.get_pin_location(pads.tx_data[n]) pad = platform.get_pin_location(pads.tx_data[n])
name = f"auto_{name}" io_prop = platform.get_pin_properties(pads.tx_data[n])
name = f"auto_{name}"
tx_data_h.append(platform.add_iface_io(name + "_HI")) tx_data_h.append(platform.add_iface_io(name + "_HI"))
tx_data_l.append(platform.add_iface_io(name + "_LO")) tx_data_l.append(platform.add_iface_io(name + "_LO"))
@ -39,6 +40,7 @@ class LiteEthPHYRGMIITX(Module):
"mode" : "OUTPUT", "mode" : "OUTPUT",
"name" : name, "name" : name,
"location" : pad, "location" : pad,
"properties" : io_prop,
"size" : 1, "size" : 1,
"out_reg" : "DDIO_RESYNC", "out_reg" : "DDIO_RESYNC",
"out_clk_pin" : "auto_eth_tx_clk", "out_clk_pin" : "auto_eth_tx_clk",
@ -71,9 +73,10 @@ class LiteEthPHYRGMIIRX(Module):
rx_data_h = [] rx_data_h = []
rx_data_l = [] rx_data_l = []
for n in range(4): for n in range(4):
name = platform.get_pin_name(pads.rx_data[n]) name = platform.get_pin_name(pads.rx_data[n])
pad = platform.get_pin_location(pads.rx_data[n]) pad = platform.get_pin_location(pads.rx_data[n])
name = f"auto_{name}" io_prop = platform.get_pin_properties(pads.rx_data[n])
name = f"auto_{name}"
rx_data_h.append(platform.add_iface_io(name + "_HI")) rx_data_h.append(platform.add_iface_io(name + "_HI"))
rx_data_l.append(platform.add_iface_io(name + "_LO")) rx_data_l.append(platform.add_iface_io(name + "_LO"))
@ -83,6 +86,7 @@ class LiteEthPHYRGMIIRX(Module):
"mode" : "INPUT", "mode" : "INPUT",
"name" : name, "name" : name,
"location" : pad, "location" : pad,
"properties" : io_prop,
"size" : 1, "size" : 1,
"in_reg" : "DDIO_RESYNC", "in_reg" : "DDIO_RESYNC",
"in_clk_pin" : "auto_eth_rx_clk", "in_clk_pin" : "auto_eth_rx_clk",
@ -124,11 +128,12 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# ------- # -------
eth_rx_clk = platform.add_iface_io("auto_eth_rx_clk") eth_rx_clk = platform.add_iface_io("auto_eth_rx_clk")
block = { block = {
"type" : "GPIO", "type" : "GPIO",
"size" : 1, "size" : 1,
"location" : platform.get_pin_location(clock_pads.rx)[0], "location" : platform.get_pin_location(clock_pads.rx)[0],
"name" : platform.get_pin_name(eth_rx_clk), "properties" : platform.get_pin_properties(clock_pads.rx),
"mode" : "INPUT_CLK" "name" : platform.get_pin_name(eth_rx_clk),
"mode" : "INPUT_CLK"
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk) self.comb += self.cd_eth_rx.clk.eq(eth_rx_clk)
@ -139,11 +144,12 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# TX Clk. # TX Clk.
# ------- # -------
block = { block = {
"type" : "GPIO", "type" : "GPIO",
"size" : 1, "size" : 1,
"location" : platform.get_pin_location(clock_pads.tx)[0], "location" : platform.get_pin_location(clock_pads.tx)[0],
"name" : "auto_eth_tx_clk_delayed", "properties" : platform.get_pin_properties(clock_pads.tx),
"mode" : "OUTPUT_CLK" "name" : "auto_eth_tx_clk_delayed",
"mode" : "OUTPUT_CLK"
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)