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core/udp: Allow adding TX/RX Buffer on interface to improve/cut timings.

This commit is contained in:
Florent Kermarrec 2024-04-04 13:08:25 +02:00
parent c250bb1485
commit d558122251
1 changed files with 14 additions and 2 deletions
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14
liteeth/core/udp.py
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@ -38,7 +38,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
self.dw = dw self.dw = dw
LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port", dw=dw) LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port", dw=dw)
def get_port(self, udp_port, dw=8, cd="sys"): def get_port(self, udp_port, dw=8, cd="sys", tx_buffer=False, rx_buffer=False):
if udp_port in self.users.keys(): if udp_port in self.users.keys():
raise ValueError("Port {0:#x} already assigned".format(udp_port)) raise ValueError("Port {0:#x} already assigned".format(udp_port))
@ -48,6 +48,12 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
# TX # TX
# --- # ---
# Buffer.
if tx_buffer:
self.tx_buffer = tx_buffer = stream.Buffer(eth_udp_user_description(user_port.dw))
self.comb += tx_buffer.source.connect(user_port.sink)
user_port.sink = tx_buffer.sink
# CDC. # CDC.
self.tx_cdc = tx_cdc = stream.ClockDomainCrossing( self.tx_cdc = tx_cdc = stream.ClockDomainCrossing(
layout = eth_udp_user_description(user_port.dw), layout = eth_udp_user_description(user_port.dw),
@ -86,6 +92,12 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
# Interface. # Interface.
self.comb += rx_cdc.source.connect(user_port.source) self.comb += rx_cdc.source.connect(user_port.source)
# Buffer.
if rx_buffer:
self.rx_buffer = rx_buffer = stream.Buffer(eth_udp_user_description(user_port.dw))
self.comb += user_port.source.connect(rx_buffer.sink)
user_port.source = rx_buffer.sink
# Expose/Return User Port. # Expose/Return User Port.
# ------------------------ # ------------------------
self.users[udp_port] = internal_port self.users[udp_port] = internal_port