Hardware/liteeth
1
0
Fork 0
mirror of https://github.com/enjoy-digital/liteeth.git synced 2025-01-03 03:43:37 -05:00
Code Issues Projects Releases Packages Wiki Activity

phy/s7rgmii: add configurable iodelay_clk_freq

Browse source
This commit is contained in:
Jędrzej Boczar 2021-04-27 10:45:55 +02:00
parent 392414eef8
commit dbc0b75178
1 changed files with 9 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
liteeth/phy/s7rgmii.py
View file

@ -59,13 +59,15 @@ class LiteEthPHYRGMIITX(Module):
class LiteEthPHYRGMIIRX(Module):
def __init__(self, pads, rx_delay=2e-9):
def __init__(self, pads, rx_delay=2e-9, iodelay_clk_freq=200e6):
self.source = source = stream.Endpoint(eth_phy_description(8))
# # #
rx_delay_taps = int(rx_delay/78e-12) # 78ps per tap with 200MHz IDELAYE2 REFCLK
assert rx_delay_taps < 32
assert iodelay_clk_freq in [200e6, 300e6, 400e6]
iodelay_tap_average = 1 / (2*32 * iodelay_clk_freq)
rx_delay_taps = round(rx_delay / iodelay_tap_average)
assert rx_delay_taps < 32, "Exceeded ODELAYE2 max value: {} >= 32".format(rx_delay_taps)
rx_ctl_ibuf = Signal()
rx_ctl_idelay = Signal()
@ -79,6 +81,7 @@ class LiteEthPHYRGMIIRX(Module):
Instance("IDELAYE2",
p_IDELAY_TYPE = "FIXED",
p_IDELAY_VALUE = rx_delay_taps,
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
i_C = 0,
i_LD = 0,
i_CE = 0,
@ -107,6 +110,7 @@ class LiteEthPHYRGMIIRX(Module):
Instance("IDELAYE2",
p_IDELAY_TYPE = "FIXED",
p_IDELAY_VALUE = rx_delay_taps,
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
i_C = 0,
i_LD = 0,
i_CE = 0,
@ -207,10 +211,10 @@ class LiteEthPHYRGMII(Module, AutoCSR):
dw = 8
tx_clk_freq = 125e6
rx_clk_freq = 125e6
def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9, iodelay_clk_freq=200e6):
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay, iodelay_clk_freq))
self.sink, self.source = self.tx.sink, self.rx.source
if hasattr(pads, "mdc"):