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phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5.

This commit is contained in:
Florent Kermarrec 2020-04-22 10:14:36 +02:00
parent 705003e523
commit dc67e6d070
1 changed files with 27 additions and 32 deletions
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59
liteeth/phy/ecp5rgmii.py
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@ -6,6 +6,8 @@
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import DDROutput, DDRInput
from liteeth.common import * from liteeth.common import *
from liteeth.phy.common import * from liteeth.phy.common import *
@ -20,13 +22,11 @@ class LiteEthPHYRGMIITX(Module):
tx_data_oddrx1f = Signal(4) tx_data_oddrx1f = Signal(4)
self.specials += [ self.specials += [
Instance("ODDRX1F", DDROutput(
i_SCLK = ClockSignal("eth_tx"), clk = ClockSignal("eth_tx"),
i_RST = ResetSignal("eth_tx"), i1 = sink.valid,
i_D0 = sink.valid, i2 = sink.valid,
i_D1 = sink.valid, o = tx_ctl_oddrx1f),
o_Q = tx_ctl_oddrx1f
),
Instance("DELAYF", Instance("DELAYF",
p_DEL_MODE = "SCLK_ALIGNED", p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY0", p_DEL_VALUE = "DELAY0",
@ -38,13 +38,11 @@ class LiteEthPHYRGMIITX(Module):
] ]
for i in range(4): for i in range(4):
self.specials += [ self.specials += [
Instance("ODDRX1F", DDROutput(
i_SCLK = ClockSignal("eth_tx"), clk = ClockSignal("eth_tx"),
i_RST = ResetSignal("eth_tx"), i1 = sink.data[i],
i_D0 = sink.data[i], i2 = sink.data[4+i],
i_D1 = sink.data[4+i], o = tx_data_oddrx1f[i]),
o_Q = tx_data_oddrx1f[i]
),
Instance("DELAYF", Instance("DELAYF",
p_DEL_MODE = "SCLK_ALIGNED", p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY0", p_DEL_VALUE = "DELAY0",
@ -83,11 +81,11 @@ class LiteEthPHYRGMIIRX(Module):
i_DIRECTION = 0, i_DIRECTION = 0,
i_A = pads.rx_ctl, i_A = pads.rx_ctl,
o_Z = rx_ctl_delayf), o_Z = rx_ctl_delayf),
Instance("IDDRX1F", DDRInput(
i_SCLK = ClockSignal("eth_rx"), clk = ClockSignal("eth_rx"),
i_RST = ResetSignal("eth_rx"), i = rx_ctl_delayf,
i_D = rx_ctl_delayf, o1 = rx_ctl,
o_Q0 = rx_ctl, o2 = Signal()
) )
] ]
self.sync += rx_ctl_reg.eq(rx_ctl) self.sync += rx_ctl_reg.eq(rx_ctl)
@ -101,12 +99,11 @@ class LiteEthPHYRGMIIRX(Module):
i_DIRECTION = 0, i_DIRECTION = 0,
i_A = pads.rx_data[i], i_A = pads.rx_data[i],
o_Z = rx_data_delayf[i]), o_Z = rx_data_delayf[i]),
Instance("IDDRX1F", DDRInput(
i_SCLK = ClockSignal("eth_rx"), clk = ClockSignal("eth_rx"),
i_RST = ResetSignal("eth_rx"), i = rx_data_delayf[i],
i_D = rx_data_delayf[i], o1 = rx_data[i],
o_Q0 = rx_data[i], o2 = rx_data[i+4]
o_Q1 = rx_data[i+4]
) )
] ]
self.sync += rx_data_reg.eq(rx_data) self.sync += rx_data_reg.eq(rx_data)
@ -143,13 +140,11 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
eth_tx_clk_o = Signal() eth_tx_clk_o = Signal()
self.specials += [ self.specials += [
Instance("ODDRX1F", DDROutput(
i_SCLK = ClockSignal("eth_tx"), clk = ClockSignal("eth_tx"),
i_RST = ResetSignal("eth_tx"), i1 = 1,
i_D0 = 1, i2 = 0,
i_D1 = 0, o = eth_tx_clk_o),
o_Q = eth_tx_clk_o
),
Instance("DELAYF", Instance("DELAYF",
p_DEL_MODE = "SCLK_ALIGNED", p_DEL_MODE = "SCLK_ALIGNED",
p_DEL_VALUE = "DELAY{}".format(tx_delay_taps), p_DEL_VALUE = "DELAY{}".format(tx_delay_taps),