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core/mac/sram: fix reception of frames larger than mtu 

-use 32bits length CSR (allow software to detect frames larger than mtu)
-drop remaining bytes larger than mtu
This commit is contained in:
Florent Kermarrec 2016-05-01 07:37:24 +02:00
parent 072969ff58
commit e1da2df97d
1 changed files with 2 additions and 3 deletions
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5
liteeth/core/mac/sram.py
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@ -4,14 +4,13 @@ from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import * from litex.soc.interconnect.csr_eventmanager import *
class LiteEthMACSRAMWriter(Module, AutoCSR): class LiteEthMACSRAMWriter(Module, AutoCSR):
def __init__(self, dw, depth, nslots=2): def __init__(self, dw, depth, nslots=2):
self.sink = sink = stream.Endpoint(eth_phy_description(dw)) self.sink = sink = stream.Endpoint(eth_phy_description(dw))
self.crc_error = Signal() self.crc_error = Signal()
slotbits = max(log2_int(nslots), 1) slotbits = max(log2_int(nslots), 1)
lengthbits = log2_int(depth*4) # length in bytes lengthbits = 32
self._slot = CSRStatus(slotbits) self._slot = CSRStatus(slotbits)
self._length = CSRStatus(lengthbits) self._length = CSRStatus(lengthbits)
@ -73,7 +72,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
) )
fsm.act("WRITE", fsm.act("WRITE",
counter_ce.eq(sink.valid), counter_ce.eq(sink.valid),
ongoing.eq(1), ongoing.eq(counter < eth_mtu),
If(sink.valid & sink.last, If(sink.valid & sink.last,
If((sink.error & sink.last_be) != 0, If((sink.error & sink.last_be) != 0,
NextState("DISCARD") NextState("DISCARD")