phy/k7_1000basex: Make CSR optional and allow external reset control.
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8680f74de0
commit
e3176c9386
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@ -49,7 +49,7 @@ class K7_1000BASEX(Module, AutoCSR):
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dw = 8
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dw = 8
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tx_clk_freq = 125e6
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tx_clk_freq = 125e6
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rx_clk_freq = 125e6
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rx_clk_freq = 125e6
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def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq):
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def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, with_csr=True):
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pcs = PCS(lsb_first=True)
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pcs = PCS(lsb_first=True)
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self.submodules += pcs
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self.submodules += pcs
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@ -66,7 +66,9 @@ class K7_1000BASEX(Module, AutoCSR):
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self.txoutclk = Signal()
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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self.rxoutclk = Signal()
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self.crg_reset = CSRStorage()
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self.crg_reset = Signal()
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if with_csr:
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self.add_csr()
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# # #
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# # #
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@ -813,7 +815,7 @@ class K7_1000BASEX(Module, AutoCSR):
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self.comb += [
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self.comb += [
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pll.reset.eq(tx_init.pllreset),
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pll.reset.eq(tx_init.pllreset),
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tx_init.plllock.eq(pll.lock),
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tx_init.plllock.eq(pll.lock),
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tx_reset.eq(tx_init.gtXxreset | self.crg_reset.storage)
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tx_reset.eq(tx_init.gtXxreset | self.crg_reset)
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]
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]
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self.sync += tx_mmcm_reset.eq(~pll.lock)
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self.sync += tx_mmcm_reset.eq(~pll.lock)
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tx_mmcm_reset.attr.add("no_retiming")
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tx_mmcm_reset.attr.add("no_retiming")
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@ -823,7 +825,7 @@ class K7_1000BASEX(Module, AutoCSR):
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self.submodules += rx_init
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self.submodules += rx_init
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self.comb += [
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self.comb += [
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rx_init.reset.eq(~tx_init.done),
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rx_init.reset.eq(~tx_init.done),
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rx_reset.eq(rx_init.gtXxreset | self.crg_reset.storage)
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rx_reset.eq(rx_init.gtXxreset | self.crg_reset)
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]
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]
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ps_restart = PulseSynchronizer("eth_tx", "sys")
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ps_restart = PulseSynchronizer("eth_tx", "sys")
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self.submodules += ps_restart
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self.submodules += ps_restart
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@ -860,3 +862,7 @@ class K7_1000BASEX(Module, AutoCSR):
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gearbox.tx_data.eq(pcs.tbi_tx),
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gearbox.tx_data.eq(pcs.tbi_tx),
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pcs.tbi_rx.eq(gearbox.rx_data)
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pcs.tbi_rx.eq(gearbox.rx_data)
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]
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]
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def add_csr(self):
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self._crg_reset = CSRStorage()
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self.comb += self.crg_reset.eq(self._crg_reset.storage)
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