phy: cleanup imports/dw

liteeth/phy/ecp5rgmii.py

@@ -1,12 +1,12 @@
-# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
 # RGMII PHY for ECP5 Lattice FPGA
-from liteeth.common import *
 
-from migen.genlib.fsm import FSM, NextState
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from liteeth.common import *
 from liteeth.phy.common import *
 
 
@@ -176,7 +176,6 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 class LiteEthPHYRGMII(Module, AutoCSR):
     dw = 8
-
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))

liteeth/phy/gmii.py

@@ -1,11 +1,11 @@
 # This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from liteeth.common import *
-
+from migen import *
 from migen.genlib.io import DDROutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from liteeth.common import *
 from liteeth.phy.common import *
 
 
@@ -82,8 +82,8 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYGMII(Module, AutoCSR):
+    dw = 8
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))

liteeth/phy/gmii_mii.py

@@ -1,16 +1,16 @@
 # This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from liteeth.common import *
-from liteeth.phy.gmii import LiteEthPHYGMIICRG
-from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
-
+from migen import *
 from migen.genlib.io import DDROutput
 from migen.genlib.cdc import PulseSynchronizer
 
 from litex.soc.interconnect.stream import Multiplexer, Demultiplexer
 
+from liteeth.common import *
+from liteeth.phy.gmii import LiteEthPHYGMIICRG
+from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 from liteeth.phy.common import LiteEthPHYMDIO
 
 
@@ -170,8 +170,8 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
 
 
 class LiteEthPHYGMIIMII(Module, AutoCSR):
+    dw = 8
     def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
-        self.dw = 8
         # Note: we can use GMII CRG since it also handles tx clock pad used for MII
         self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
         mode = self.mode_detection.mode

liteeth/phy/mii.py

@@ -1,10 +1,10 @@
 # This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from liteeth.common import *
-
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from liteeth.common import *
 from liteeth.phy.common import *
 
 
@@ -90,8 +90,8 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYMII(Module, AutoCSR):
+    dw = 8
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx =  ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYMIIRX(pads))

liteeth/phy/model.py

@@ -1,7 +1,7 @@
 # This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-import os
+from migen import *
 
 from liteeth.common import *
 
@@ -27,8 +27,8 @@ class LiteEthPHYModelCRG(Module, AutoCSR):
 
 
 class LiteEthPHYModel(Module, AutoCSR):
+    dw = 8
     def __init__(self, pads):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYModelCRG()
         self.sink = sink = stream.Endpoint(eth_phy_description(8))
         self.source = source = stream.Endpoint(eth_phy_description(8))

liteeth/phy/rmii.py

@@ -1,13 +1,12 @@
 # This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from liteeth.common import *
-
+from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
 from migen.genlib.io import DDROutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from liteeth.common import *
 from liteeth.phy.common import *
 
 
@@ -119,8 +118,8 @@ class LiteEthPHYRMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYRMII(Module, AutoCSR):
+    dw = 8
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads))

liteeth/phy/s6rgmii.py

@@ -1,12 +1,12 @@
-# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
 # RGMII PHY for Spartan6 Xilinx FPGA
-from liteeth.common import *
 
-from migen.genlib.fsm import FSM, NextState
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from liteeth.common import *
 from liteeth.phy.common import *
 
 
@@ -247,7 +247,6 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 class LiteEthPHYRGMII(Module, AutoCSR):
     dw = 8
-
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))

liteeth/phy/s7rgmii.py

@@ -2,14 +2,11 @@
 # License: BSD
 
 # RGMII PHY for 7-Series Xilinx FPGA
-from liteeth.common import *
-
-from migen.genlib.io import DDROutput
-from migen.genlib.misc import WaitTimer
-from migen.genlib.fsm import FSM, NextState
 
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from liteeth.common import *
 from liteeth.phy.common import *
 
 
@@ -152,7 +149,6 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 class LiteEthPHYRGMII(Module, AutoCSR):
     dw = 8
-
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))

liteeth/phy/usrgmii.py

@@ -3,6 +3,7 @@
 
 # RGMII PHY for Ultrascale Xilinx FPGAs
 
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from liteeth.common import *
@@ -192,7 +193,6 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 class LiteEthPHYRGMII(Module, AutoCSR):
     dw = 8
-
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))