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phy/ecp5rgmii: improve presentation

This commit is contained in:
Florent Kermarrec 2020-01-17 08:35:15 +01:00
parent 73bd27b506
commit e5c4ee7065
1 changed files with 21 additions and 21 deletions
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42
liteeth/phy/ecp5rgmii.py
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@ -16,42 +16,42 @@ class LiteEthPHYRGMIITX(Module):
# # #
tx_ctl_oddrx1f = Signal()
tx_ctl_oddrx1f = Signal()
tx_data_oddrx1f = Signal(4)
self.specials += [
Instance("ODDRX1F",
i_D0=sink.valid,
i_D1=sink.valid,
i_SCLK=ClockSignal("eth_tx"),
i_RST=ResetSignal("eth_tx"),
i_D0=sink.valid,
i_D1=sink.valid,
o_Q=tx_ctl_oddrx1f
),
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY0",
i_A=tx_ctl_oddrx1f,
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=tx_ctl_oddrx1f,
o_Z=pads.tx_ctl)
]
for i in range(4):
self.specials += [
Instance("ODDRX1F",
i_D0=sink.data[i],
i_D1=sink.data[4+i],
i_SCLK=ClockSignal("eth_tx"),
i_RST=ResetSignal("eth_tx"),
i_D0=sink.data[i],
i_D1=sink.data[4+i],
o_Q=tx_data_oddrx1f[i]
),
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY0",
i_A=tx_data_oddrx1f[i],
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=tx_data_oddrx1f[i],
o_Z=pads.tx_data[i])
]
self.comb += sink.ready.eq(1)
@ -63,26 +63,26 @@ class LiteEthPHYRGMIIRX(Module):
# # #
rx_ctl_delayf = Signal()
rx_ctl = Signal()
rx_ctl_reg = Signal()
rx_ctl_delayf = Signal()
rx_ctl = Signal()
rx_ctl_reg = Signal()
rx_data_delayf = Signal(4)
rx_data = Signal(8)
rx_data_reg = Signal(8)
rx_data = Signal(8)
rx_data_reg = Signal(8)
self.specials += [
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY{}".format(int(2e-9/25e-12)), # 2ns (25ps per tap)
i_A=pads.rx_ctl,
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=pads.rx_ctl,
o_Z=rx_ctl_delayf),
Instance("IDDRX1F",
i_D=rx_ctl_delayf,
i_SCLK=ClockSignal("eth_rx"),
i_RST=ResetSignal("eth_rx"),
i_D=rx_ctl_delayf,
o_Q0=rx_ctl,
)
]
@ -92,15 +92,15 @@ class LiteEthPHYRGMIIRX(Module):
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY{}".format(int(2e-9/25e-12)), # 2ns (25ps per tap)
i_A=pads.rx_data[i],
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=pads.rx_data[i],
o_Z=rx_data_delayf[i]),
Instance("IDDRX1F",
i_D=rx_data_delayf[i],
i_SCLK=ClockSignal("eth_rx"),
i_RST=ResetSignal("eth_rx"),
i_D=rx_data_delayf[i],
o_Q0=rx_data[i],
o_Q1=rx_data[i+4]
)
@ -137,19 +137,19 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
eth_tx_clk_o = Signal()
self.specials += [
Instance("ODDRX1F",
i_D0=1,
i_D1=0,
i_SCLK=ClockSignal("eth_tx"),
i_RST=ResetSignal("eth_tx"),
i_D0=1,
i_D1=0,
o_Q=eth_tx_clk_o
),
Instance("DELAYF",
p_DEL_MODE="SCLK_ALIGNED",
p_DEL_VALUE="DELAY{}".format(int(2e-9/25e-12)),
i_A=eth_tx_clk_o,
i_LOADN=1,
i_MOVE=0,
i_DIRECTION=0,
i_A=eth_tx_clk_o,
o_Z=clock_pads.tx)
]
@ -172,8 +172,8 @@ class LiteEthPHYRGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source
if hasattr(pads, "mdc"):