example/udp_loopback: simplify/cleanup and make it more generic
This commit is contained in:
Florent Kermarrec
parent
50cc7d0671
commit
e980b603cc
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## Purpose
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Example of UDP loopback with LiteETH IP/UDP hardware stack. The FPGA will echo back any UDP packet it
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receives on the specified port (default=8000) to the sender.
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You can also found a detailed tutorial [here](https://yehowshuaimmanuel.com/fpga/migen/ethernet_ecp5/).
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## Usage
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#!bash
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./versa_ecp5.py
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./versa_ecp5.py load
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The IP address assigned to the FPGA in this example is ``192.168.1.50`` and the Host is expected to
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be configured with ``192.168.1.100``. Since ``192.168.1.XXX`` is a common address in home networks, a
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collisiton is quite possible and in this case, you will need to re-configure the FPGA and the python
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scripts accordingly.
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Once you are able to ping the FPGA board from your computer, you can run the sender and listener scripts
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and should see the date/time UDP packets emitted by the sender looped back to the the listener:
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#!bash
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$python3 listener.py &
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$python3 sender.py
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2019-11-20 08:31:00
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2019-11-20 08:31:01
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2019-11-20 08:31:01
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2019-11-20 08:31:02
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2019-11-20 08:31:02
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2019-11-20 08:31:03
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2019-11-20 08:31:03
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2019-11-20 08:31:04
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2019-11-20 08:31:04
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[...]
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# License: BSD
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import socket
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UDP_IP = "192.168.1.50"
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UDP_PORT = 8000
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sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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sock.bind((UDP_IP, UDP_PORT))
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while True:
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data, addr = sock.recvfrom(1024)
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print(data.decode("utf-8"))
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# License: BSD
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import socket
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import time
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import datetime
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UDP_IP = "192.168.1.100"
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UDP_PORT = 8000
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sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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while True:
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t = datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S")
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print(t)
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sock.sendto(t.encode('utf-8'), (UDP_IP, UDP_PORT))
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time.sleep(0.5)
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.boards.platforms import versa_ecp5
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.common import *
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.core import LiteEthUDPIPCore
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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# clk / rst
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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# pll
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# UDPLoopback ------------------------------------------------------------------------------------------
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class UDPLoopback(SoCMini):
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def __init__(self, platform):
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sys_clk_freq = int(150e6)
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SoCMini.__init__(self, platform, sys_clk_freq, ident="UDPLoopback", ident_version=True)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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self.submodules.eth_phy = LiteEthPHYRGMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_csr("eth_phy")
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# core
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self.submodules.eth_core = LiteEthUDPIPCore(
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phy = self.eth_phy,
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mac_address = 0x10e2d5000000,
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ip_address = "192.168.1.50",
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clk_freq = sys_clk_freq)
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# add udp loopback on port 6000 with dw=8
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self.add_udp_loopback(6000, 8, 128, "loopback_8")
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# add udp loopback on port 8000 with dw=32
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self.add_udp_loopback(8000, 32, 128, "loopback_32")
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# timing constraints
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self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep")
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self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9/125e6)
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def add_udp_loopback(self, port, dw, depth, name=None):
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port = self.eth_core.udp.crossbar.get_port(port, dw)
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buf = stream.SyncFIFO(eth_udp_user_description(dw), depth//(dw//8))
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if name is None:
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self.submodules += buf
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else:
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setattr(self.submodules, name, buf)
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self.comb += Port.connect(port, buf)
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# Load ---------------------------------------------------------------------------------------------
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def load():
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import os
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f = open("ecp5-versa5g.cfg", "w")
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f.write(
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"""
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
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""")
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f.close()
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os.system("openocd -f ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/gateware/top.svf; exit\"")
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# Build --------------------------------------------------------------------------------------------
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def main():
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if "load" in sys.argv[1:]:
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load()
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exit()
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else:
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platform = versa_ecp5.Platform(toolchain="trellis")
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soc = UDPLoopback(platform)
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builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
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vns = builder.build()
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if __name__ == "__main__":
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main()
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## Purpose
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Example of UDP loopback on versa ECP5 FPGA using the Liteeth UDP module.
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The FPGA will echo back any UDP packet it recieves over RJ45 ethernet to the sender.
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You can also view a rather detailed tutorial [here](https://yehowshuaimmanuel.com/fpga/migen/ethernet_ecp5/).
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## Usage
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#!bash
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./udp.py build
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./udp.py load
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You will have to configure your ARP table manually since this example does not instantiate the Liteeth ARP module table.
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The IP address assigned to the FPGA in this example is ``169.253.2.100``. You should make sure that your computer's
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ethernet interface is on the same subnet, for example:
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#!bash
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$ifconfig en7 192.168.1.100 netmask 255.255.255.0
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And then after that configure your ARP table:
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#!bash
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$arp -s 192.168.1.50 10:e2:d5:00:00:00 -iface en7
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You should now be able to send and recieve UDP packets.
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#!bash
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$python3 listener.py &
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$python3 sender.py
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UDP target IP:192.168.1.50
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UDP target port:8000
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message:Hey.
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received message:b'Heyn'
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If everything is working, you should be able to see the ``received message`` line as shown above.
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## Possible Problems
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192.168.1.XXX is a common address in home networks a collsion is quite possible.
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In particular, some ARP daemons will automatically add a higher priority duplicate IP entry for 192.168.1.50 to the Wi-Fi
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interface making it challenging to route packets with the ethernet as the gateway.
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To get around this, change the IP address of your ethernet and FPGA to something different from 192. You must change this
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in in all the Python files in this directory.
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# License: BSD
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import socket
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UDP_IP = "192.168.1.100"
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UDP_PORT = 8000
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sock = socket.socket(socket.AF_INET, # Internet
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socket.SOCK_DGRAM) # UDP
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sock.bind((UDP_IP, UDP_PORT))
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while True:
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data, addr = sock.recvfrom(1024) # buffer size is 1024 bytes
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print("received message:" + str(data))
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# License: BSD
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import socket
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UDP_IP = "192.168.1.50"
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UDP_PORT = 8000
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MESSAGE = "Hey."
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print("UDP target IP:" + str(UDP_IP))
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print("UDP target port:" + str(UDP_PORT))
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print("message:" + str(MESSAGE))
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sock = socket.socket(socket.AF_INET, # Internet
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socket.SOCK_DGRAM) # UDP
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sock.sendto(MESSAGE.encode('utf-8'), (UDP_IP, UDP_PORT))
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# License: BSD
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex.boards.platforms import versa_ecp5
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.common import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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# clk / rst
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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# pll
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# UDPLoopback ------------------------------------------------------------------------------------------
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class UDPLoopback(SoCMini):
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def __init__(self, platform):
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sys_clk_freq = int(150e6)
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SoCMini.__init__(self, platform, sys_clk_freq, ident="UDPLoopback", ident_version=True)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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self.submodules.eth_phy = LiteEthPHYRGMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_csr("eth_phy")
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# core
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self.submodules.eth_core = LiteEthUDPIPCore(
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phy = self.eth_phy,
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mac_address = 0x10e2d5000000,
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ip_address = "192.168.1.50",
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clk_freq = sys_clk_freq)
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# add udp loopback on port 6000 with dw=8
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self.add_udp_loopback(6000, 8, 128, "loopback_8")
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# add udp loopback on port 8000 with dw=32
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self.add_udp_loopback(8000, 32, 128, "loopback_32")
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# timing constraints - generates top.lpf
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self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep")
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self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9/125e6)
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def add_udp_loopback(self, port, dw, depth, name=None):
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port = self.eth_core.udp.crossbar.get_port(port, dw)
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buf = stream.SyncFIFO(eth_udp_user_description(dw), depth//(dw//8))
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if name is None:
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self.submodules += buf
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else:
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setattr(self.submodules, name, buf)
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self.comb += Port.connect(port, buf)
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# Load ---------------------------------------------------------------------------------------------
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def load():
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import os
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f = open("ecp5-versa5g.cfg", "w")
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f.write(
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"""
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
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""")
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f.close()
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os.system("openocd -f ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/gateware/top.svf; exit\"")
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# Build --------------------------------------------------------------------------------------------
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def main():
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if "load" in sys.argv[1:]:
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load()
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exit()
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if "build" in sys.argv[1:]:
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platform = versa_ecp5.Platform(toolchain="trellis")
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soc = UDPLoopback(platform)
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builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
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vns = builder.build()
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else:
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print("Usage:")
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print("./udp.py build")
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print("./udp.py load")
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if __name__ == "__main__":
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main()
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