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liteeth_gen: improve readability and add clk_freq checks.

This commit is contained in:
Florent Kermarrec 2020-03-19 19:55:27 +01:00
parent 693a6b1513
commit ea24ff6993
1 changed files with 29 additions and 6 deletions
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33
liteeth/gen.py
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@ -171,6 +171,7 @@ class PHYCore(SoCMini):
if deprecated in core_config: if deprecated in core_config:
raise RuntimeWarning("Config option {!r} is now a sub-option of 'soc'".format(deprecated)) raise RuntimeWarning("Config option {!r} is now a sub-option of 'soc'".format(deprecated))
# SoC parameters ---------------------------------------------------------------------------
soc_args = {} soc_args = {}
if "soc" in core_config: if "soc" in core_config:
soc_config = core_config["soc"] soc_config = core_config["soc"]
@ -181,28 +182,35 @@ class PHYCore(SoCMini):
else: else:
soc_args[arg] = soc_config[arg] soc_args[arg] = soc_config[arg]
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args) SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clock"), self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset")) platform.request("sys_reset"))
# PHY --------------------------------------------------------------------------------------
phy = core_config["phy"] phy = core_config["phy"]
# ethernet
if phy in [liteeth_phys.LiteEthPHYMII]: if phy in [liteeth_phys.LiteEthPHYMII]:
assert self.clk_freq >= 12.5e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("mii_eth_clocks"), clock_pads = platform.request("mii_eth_clocks"),
pads = platform.request("mii_eth")) pads = platform.request("mii_eth"))
elif phy in [liteeth_phys.LiteEthPHYRMII]: elif phy in [liteeth_phys.LiteEthPHYRMII]:
assert self.clk_freq >= 12.5e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("rmii_eth_clocks"), clock_pads = platform.request("rmii_eth_clocks"),
pads = platform.request("rmii_eth")) pads = platform.request("rmii_eth"))
elif phy in [liteeth_phys.LiteEthPHYGMII]: elif phy in [liteeth_phys.LiteEthPHYGMII]:
assert self.clk_freq >= 125e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("gmii_eth_clocks"), clock_pads = platform.request("gmii_eth_clocks"),
pads = platform.request("gmii_eth")) pads = platform.request("gmii_eth"))
elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]: elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]:
assert self.clk_freq >= 125e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("rgmii_eth_clocks"), clock_pads = platform.request("rgmii_eth_clocks"),
pads = platform.request("rgmii_eth")) pads = platform.request("rgmii_eth"),
with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
else: else:
raise ValueError("Unsupported PHY"); raise ValueError("Unsupported PHY");
self.submodules.ethphy = ethphy self.submodules.ethphy = ethphy
@ -212,13 +220,20 @@ class PHYCore(SoCMini):
class MACCore(PHYCore): class MACCore(PHYCore):
def __init__(self, platform, core_config): def __init__(self, platform, core_config):
# PHY --------------------------------------------------------------------------------------
PHYCore.__init__(self, platform, core_config) PHYCore.__init__(self, platform, core_config)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"]) # MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac") self.add_csr("ethmac")
# Wishbone Interface -----------------------------------------------------------------------
class _WishboneBridge(Module): class _WishboneBridge(Module):
def __init__(self, interface): def __init__(self, interface):
self.wishbone = interface self.wishbone = interface
@ -228,15 +243,23 @@ class MACCore(PHYCore):
self.submodules += bridge self.submodules += bridge
self.add_wb_master(bridge.wishbone) self.add_wb_master(bridge.wishbone)
# Interrupt Interface ----------------------------------------------------------------------
self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq) self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
# UDP Core ----------------------------------------------------------------------------------------- # UDP Core -----------------------------------------------------------------------------------------
class UDPCore(PHYCore): class UDPCore(PHYCore):
def __init__(self, platform, core_config): def __init__(self, platform, core_config):
# PHY --------------------------------------------------------------------------------------
PHYCore.__init__(self, platform, core_config) PHYCore.__init__(self, platform, core_config)
self.submodules.core = LiteEthUDPIPCore(self.ethphy, core_config["mac_address"], convert_ip(core_config["ip_address"]), core_config["clk_freq"]) # Core -------------------------------------------------------------------------------------
self.submodules.core = LiteEthUDPIPCore(self.ethphy,
mac_address = core_config["mac_address"],
ip_address = core_config["ip_address"],
clk_freq = core_config["clk_freq"])
# UDP --------------------------------------------------------------------------------------
udp_port = self.core.udp.crossbar.get_port(core_config["port"], 8) udp_port = self.core.udp.crossbar.get_port(core_config["port"], 8)
# XXX avoid manual connect # XXX avoid manual connect
udp_sink = self.platform.request("udp_sink") udp_sink = self.platform.request("udp_sink")