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mac/__init__.py: Improve/Cleanup LiteEthMAC.

This commit is contained in:
Florent Kermarrec 2024-08-19 10:19:53 +02:00
parent bfc07e543a
commit edc7188faa
1 changed files with 30 additions and 18 deletions
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46
liteeth/mac/__init__.py
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@ -36,6 +36,8 @@ class LiteEthMAC(LiteXModule):
assert interface in ["crossbar", "wishbone", "hybrid"] assert interface in ["crossbar", "wishbone", "hybrid"]
assert endianness in ["big", "little"] assert endianness in ["big", "little"]
# Core.
# -----
self.core = LiteEthMACCore( self.core = LiteEthMACCore(
phy = phy, phy = phy,
dw = dw, dw = dw,
@ -47,7 +49,10 @@ class LiteEthMAC(LiteXModule):
rx_cdc_buffered = rx_cdc_buffered, rx_cdc_buffered = rx_cdc_buffered,
) )
self.csrs = [] self.csrs = []
if interface == "crossbar":
# Crossbar Mode.
# --------------
if interface in ["crossbar"]:
self.crossbar = LiteEthMACCrossbar(dw) self.crossbar = LiteEthMACCrossbar(dw)
self.packetizer = LiteEthMACPacketizer(dw) self.packetizer = LiteEthMACPacketizer(dw)
self.depacketizer = LiteEthMACDepacketizer(dw) self.depacketizer = LiteEthMACDepacketizer(dw)
@ -57,8 +62,11 @@ class LiteEthMAC(LiteXModule):
self.core.source.connect(self.depacketizer.sink), self.core.source.connect(self.depacketizer.sink),
self.depacketizer.source.connect(self.crossbar.master.sink) self.depacketizer.source.connect(self.crossbar.master.sink)
] ]
else: # Wishbone/Hybrid Mode.
# Wishbone MAC # ---------------------
if interface in ["wishbone", "hybrid"]:
# Wishbone MAC (Common to Wishbone and Hybrid Modes).
# ---------------------------------------------------
self.rx_slots = CSRConstant(nrxslots) self.rx_slots = CSRConstant(nrxslots)
self.tx_slots = CSRConstant(ntxslots) self.tx_slots = CSRConstant(ntxslots)
self.slot_size = CSRConstant(2**bits_for(eth_mtu)) self.slot_size = CSRConstant(2**bits_for(eth_mtu))
@ -69,25 +77,29 @@ class LiteEthMAC(LiteXModule):
endianness = endianness, endianness = endianness,
timestamp = timestamp, timestamp = timestamp,
) )
# On some targets (Intel/Altera), the complex ports aren't inferred
# as block ram, but are created with LUTs. FullMemoryWe splits such
# `Memory` instances up into 4 separate memory blocks, each
# containing 8 bits which gets inferred correctly on intel/altera.
# Yosys on ECP5 inferrs the original correctly, so FullMemoryWE
# leads to additional block ram instances being used, which
# increases memory usage by a lot.
if full_memory_we: if full_memory_we:
wishbone_interface = FullMemoryWE()(wishbone_interface) wishbone_interface = self.apply_full_memory_we(wishbone_interface)
self.interface = wishbone_interface self.interface = wishbone_interface
self.ev, self.bus_rx, self.bus_tx = self.interface.sram.ev, self.interface.bus_rx, self.interface.bus_tx self.ev = self.interface.sram.ev
self.bus_rx = self.interface.bus_rx
self.bus_tx = self.interface.bus_tx
self.csrs = self.interface.get_csrs() + self.core.get_csrs() self.csrs = self.interface.get_csrs() + self.core.get_csrs()
if interface == "hybrid":
# Hardware MAC # Wishbone Mode.
self.crossbar = LiteEthMACCrossbar(dw) # --------------
self.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, hw_mac) if interface in ["wishbone"]:
else:
self.comb += self.interface.source.connect(self.core.sink) self.comb += self.interface.source.connect(self.core.sink)
self.comb += self.core.source.connect(self.interface.sink) self.comb += self.core.source.connect(self.interface.sink)
# Hybrid Mode.
# ------------
if interface in ["hybrid"]:
self.crossbar = LiteEthMACCrossbar(dw)
self.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, hw_mac)
def apply_full_memory_we(self, interface):
# FullMemoryWE splits memory into 8-bit blocks to ensure proper block RAM inference on most FPGAs.
# On some (e.g., ECP5/Yosys), this isn't needed and can increase memory usage.
return FullMemoryWE()(wishbone_interface)
def get_csrs(self): def get_csrs(self):
return self.csrs return self.csrs