Merge pull request #174 from enjoy-digital/1000basex_fixes_cleanup
1000basex fixes cleanup.
This commit is contained in:
commit
efcbebe558
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@ -90,7 +90,7 @@ class A7_1000BASEX(LiteXModule):
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# RX Byte and Word Alignment Attributes
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p_ALIGN_COMMA_DOUBLE = "FALSE",
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p_ALIGN_COMMA_ENABLE = 0b1111111111,
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p_ALIGN_COMMA_WORD = 1,
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p_ALIGN_COMMA_WORD = 2,
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p_ALIGN_MCOMMA_DET = "TRUE",
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p_ALIGN_MCOMMA_VALUE = 0b1010000011,
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p_ALIGN_PCOMMA_DET = "TRUE",
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@ -212,7 +212,7 @@ class A7_1000BASEX(LiteXModule):
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# CDR Attributes
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p_RXCDR_CFG = {
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1.25e9 : 0x0001107FE086021101010,
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1.25e9 : 0x0000107FE106001041010,
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3.125e9 : 0x0000107FE206001041010,
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}[self.linerate],
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p_RXCDR_FR_RESET_ON_EIDLE = 0b0,
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@ -505,9 +505,9 @@ class A7_1000BASEX(LiteXModule):
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o_RXBYTEISALIGNED = Open(),
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o_RXBYTEREALIGN = Open(),
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o_RXCOMMADET = Open(),
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i_RXCOMMADETEN = 0,
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i_RXMCOMMAALIGNEN = 0,
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i_RXPCOMMAALIGNEN = 0,
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i_RXCOMMADETEN = 0b1,
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i_RXMCOMMAALIGNEN = pcs.align,
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i_RXPCOMMAALIGNEN = pcs.align,
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i_RXSLIDE = 0,
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# Receive Ports - RX Channel Bonding Ports
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o_RXCHANBONDSEQ = Open(),
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@ -484,9 +484,9 @@ class K7_1000BASEX(LiteXModule):
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o_RXBYTEISALIGNED = Open(),
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o_RXBYTEREALIGN = Open(),
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o_RXCOMMADET = Open(),
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i_RXCOMMADETEN = 1,
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i_RXMCOMMAALIGNEN = 1,
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i_RXPCOMMAALIGNEN = 1,
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i_RXCOMMADETEN = 0b1,
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i_RXMCOMMAALIGNEN = pcs.align,
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i_RXPCOMMAALIGNEN = pcs.align,
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# Receive Ports - RX Channel Bonding Ports
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o_RXCHANBONDSEQ = Open(),
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@ -536,7 +536,7 @@ class KU_1000BASEX(LiteXModule):
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i_RXCHBONDLEVEL = 0b000,
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i_RXCHBONDMASTER = 0b0,
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i_RXCHBONDSLAVE = 0b0,
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i_RXCOMMADETEN = 0b0,
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i_RXCOMMADETEN = 0b1,
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i_RXDFEAGCCTRL = 0b01,
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i_RXDFEAGCHOLD = 0b0,
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i_RXDFEAGCOVRDEN = 0b0,
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@ -593,7 +593,7 @@ class KU_1000BASEX(LiteXModule):
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i_RXLPMLFKLOVRDEN = 0b0,
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i_RXLPMOSHOLD = 0b0,
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i_RXLPMOSOVRDEN = 0b0,
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i_RXMCOMMAALIGNEN = 0b0,
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i_RXMCOMMAALIGNEN = pcs.align,
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i_RXMONITORSEL = 0b00,
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i_RXOOBRESET = 0b0,
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i_RXOSCALRESET = 0b0,
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@ -606,7 +606,7 @@ class KU_1000BASEX(LiteXModule):
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i_RXOSINTTESTOVRDEN = 0b0,
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i_RXOSOVRDEN = 0b0,
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i_RXOUTCLKSEL = 0b101,
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i_RXPCOMMAALIGNEN = 0b0,
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i_RXPCOMMAALIGNEN = pcs.align,
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i_RXPCSRESET = 0b0,
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i_RXPD = 0b00,
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i_RXPHALIGNEN = 0b0,
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@ -19,244 +19,11 @@ from litex.soc.cores.code_8b10b import K, D, Encoder, Decoder
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from liteeth.common import *
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# PCS TX -------------------------------------------------------------------------------------------
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# PCS Constants / Helpers --------------------------------------------------------------------------
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class PCSTX(LiteXModule):
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def __init__(self, lsb_first=False):
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self.config_valid = Signal()
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self.config_reg = Signal(16)
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self.tx_valid = Signal()
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self.tx_ready = Signal()
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self.tx_data = Signal(8)
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self.encoder = Encoder(lsb_first=lsb_first)
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# SGMII Speed Adaptation
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self.sgmii_speed = Signal(2)
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# # #
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parity = Signal()
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c_type = Signal()
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self.sync += parity.eq(~parity)
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config_reg_buffer = Signal(16)
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load_config_reg_buffer = Signal()
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self.sync += If(load_config_reg_buffer, config_reg_buffer.eq(self.config_reg))
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# Timer for SGMII data rates.
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timer = Signal(max=1000)
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timer_en = Signal()
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self.sync += [
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If(~timer_en | (timer == 0),
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If(self.sgmii_speed == 0b00,
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timer.eq(99)
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).Elif(self.sgmii_speed == 0b01,
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timer.eq(9)
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).Elif(self.sgmii_speed == 0b10,
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timer.eq(0)
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)
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).Elif(timer_en,
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timer.eq(timer - 1)
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)
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]
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self.fsm = fsm = FSM()
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fsm.act("START",
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If(self.config_valid,
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self.tx_ready.eq(1), # Discard TX data if we are in config_reg phase.
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load_config_reg_buffer.eq(1),
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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NextState("CONFIG_D")
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).Else(
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If(self.tx_valid,
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# The first byte sent is replaced by /S/.
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self.tx_ready.eq((timer == 0)),
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timer_en.eq(1),
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(27, 7)),
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NextState("DATA")
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).Else(
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self.tx_ready.eq(1), # Discard TX data.
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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NextState("IDLE")
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)
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)
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)
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fsm.act("CONFIG_D",
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If(c_type,
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self.encoder.d[0].eq(D(2, 2))
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).Else(
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self.encoder.d[0].eq(D(21, 5))
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),
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NextValue(c_type, ~c_type),
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NextState("CONFIG_REG_LSB")
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),
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fsm.act("CONFIG_REG_LSB",
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self.encoder.d[0].eq(config_reg_buffer[:8]),
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NextState("CONFIG_REG_MSB")
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)
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fsm.act("CONFIG_REG_MSB",
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self.encoder.d[0].eq(config_reg_buffer[8:]),
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NextState("START")
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)
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fsm.act("IDLE",
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# Due to latency in the encoder, we read here the disparity
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# just before the K28.5 was sent. K28.5 flips the disparity.
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If(self.encoder.disparity[0],
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# Correcting /I1/ (D5.6 preserves the disparity).
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self.encoder.d[0].eq(D(5, 6))
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).Else(
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# Preserving /I2/ (D16.2 flips the disparity).
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self.encoder.d[0].eq(D(16, 2))
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),
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NextState("START")
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)
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fsm.act("DATA",
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If(self.tx_valid,
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self.tx_ready.eq((timer == 0)),
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timer_en.eq(1),
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self.encoder.d[0].eq(self.tx_data)
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).Else(
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self.tx_ready.eq(1),
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# /T/
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(29, 7)),
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NextState("CARRIER_EXTEND_1")
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)
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)
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fsm.act("CARRIER_EXTEND_1",
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# /R/
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(23, 7)),
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If(parity,
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NextState("START")
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).Else(
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NextState("CARRIER_EXTEND_2")
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)
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)
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fsm.act("CARRIER_EXTEND_2",
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# /R/
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(23, 7)),
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NextState("START")
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)
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# PCS RX -------------------------------------------------------------------------------------------
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class PCSRX(LiteXModule):
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def __init__(self, lsb_first=False):
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self.rx_en = Signal()
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self.rx_data = Signal(8)
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self.seen_valid_ci = Signal()
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self.seen_config_reg = Signal()
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self.config_reg = Signal(16)
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self.decoder = Decoder(lsb_first=lsb_first)
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# SGMII Speed Adaptation.
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self.sgmii_speed = Signal(2)
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self.sample_en = Signal()
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# # #
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config_reg_lsb = Signal(8)
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load_config_reg_lsb = Signal()
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load_config_reg_msb = Signal()
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self.sync += [
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self.seen_config_reg.eq(0),
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If(load_config_reg_lsb,
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config_reg_lsb.eq(self.decoder.d)
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),
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If(load_config_reg_msb,
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self.config_reg.eq(Cat(config_reg_lsb, self.decoder.d)),
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self.seen_config_reg.eq(1)
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)
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]
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first_preamble_byte = Signal()
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self.comb += self.rx_data.eq(Mux(first_preamble_byte, 0x55, self.decoder.d))
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# Timer for SGMII data rates.
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timer = Signal(max=1000)
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timer_en = Signal()
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self.sync += [
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If(~timer_en | (timer == 0),
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If(self.sgmii_speed == 0b00,
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timer.eq(99)
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).Elif(self.sgmii_speed == 0b01,
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timer.eq(9)
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).Elif(self.sgmii_speed == 0b10,
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timer.eq(0)
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)
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).Elif(timer_en,
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timer.eq(timer - 1)
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)
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]
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# Speed adaptation
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self.comb += self.sample_en.eq(self.rx_en & (timer == 0))
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self.fsm = fsm = FSM()
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fsm.act("START",
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If(self.decoder.k,
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If(self.decoder.d == K(28, 5),
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NextState("K28_5")
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),
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If(self.decoder.d == K(27, 7),
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self.rx_en.eq(1),
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timer_en.eq(1),
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first_preamble_byte.eq(1),
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NextState("DATA")
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)
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)
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)
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fsm.act("K28_5",
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NextState("START"),
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If(~self.decoder.k,
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If((self.decoder.d == D(21, 5)) | (self.decoder.d == D(2, 2)),
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self.seen_valid_ci.eq(1),
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NextState("CONFIG_REG_LSB")
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),
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If((self.decoder.d == D(5, 6)) | (self.decoder.d == D(16, 2)),
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# idle
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self.seen_valid_ci.eq(1),
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NextState("START")
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),
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)
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)
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fsm.act("CONFIG_REG_LSB",
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If(self.decoder.k,
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If(self.decoder.d == K(27, 7),
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self.rx_en.eq(1),
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timer_en.eq(1),
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first_preamble_byte.eq(1),
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NextState("DATA")
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).Else(
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NextState("START") # error
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)
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).Else(
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load_config_reg_lsb.eq(1),
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NextState("CONFIG_REG_MSB")
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)
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)
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fsm.act("CONFIG_REG_MSB",
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If(~self.decoder.k,
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load_config_reg_msb.eq(1)
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),
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NextState("START")
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)
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fsm.act("DATA",
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If(self.decoder.k,
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NextState("START")
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).Else(
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self.rx_en.eq(1),
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timer_en.eq(1)
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)
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)
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SGMII_1000MBPS_SPEED = 0b10
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SGMII_100MBPS_SPEED = 0b01
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SGMII_10MBPS_SPEED = 0b00
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# PCS Gearbox --------------------------------------------------------------------------------------
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|
@ -287,8 +54,222 @@ class PCSGearbox(LiteXModule):
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phase_half.eq(~phase_half),
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]
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# PCS TX -------------------------------------------------------------------------------------------
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class PCSTX(LiteXModule):
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def __init__(self, lsb_first=False):
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self.config_valid = Signal() # Config valid.
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self.config_reg = Signal(16) # Config register (16-bit).
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self.sgmii_speed = Signal(2) # SGMII speed.
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self.sink = sink = stream.Endpoint([("data", 8)]) # Data input.
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self.encoder = Encoder(lsb_first=lsb_first) # 8b/10b Encoder.
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# Signals.
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# --------
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count = Signal() # Byte counter for config register.
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parity = Signal() # Parity for /R/ extension.
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ctype = Signal() # Toggles config type.
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# SGMII Timer.
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# ------------
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timer = Signal(max=100)
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timer_done = Signal()
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timer_enable = Signal()
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self.comb += timer_done.eq(timer == 0)
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self.sync += [
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timer.eq(timer - 1),
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If(~timer_enable | timer_done,
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Case(self.sgmii_speed, {
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SGMII_10MBPS_SPEED : timer.eq(99),
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SGMII_100MBPS_SPEED : timer.eq(9),
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SGMII_1000MBPS_SPEED : timer.eq(0),
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})
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)
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]
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# FSM.
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# ----
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self.fsm = fsm = FSM()
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fsm.act("START",
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(28, 5)),
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# Wait for valid Config.
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If(self.config_valid,
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NextValue(count, 0),
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NextState("CONFIG-D")
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# Wait for valid Data.
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).Else(
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If(sink.valid,
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self.encoder.d[0].eq(K(27, 7)), # Start-of-packet /S/.
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NextState("DATA")
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).Else(
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NextState("IDLE")
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)
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)
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)
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fsm.act("CONFIG-D",
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# Send Configuration Word.
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Case(ctype, {
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0b0 : self.encoder.d[0].eq(D(21, 5)), # /C1/.
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0b1 : self.encoder.d[0].eq(D( 2, 2)), # /C2/.
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}),
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NextValue(ctype, ~ctype),
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NextState("CONFIG-REG")
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),
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fsm.act("CONFIG-REG",
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# Send Configuration Register.
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NextValue(count, count + 1),
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Case(count, {
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0 : self.encoder.d[0].eq(self.config_reg[:8]), # LSB.
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1 : self.encoder.d[0].eq(self.config_reg[8:]), # MSB.
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}),
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If(count == (2 - 1), NextState("START"))
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)
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fsm.act("IDLE",
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# Send Idle words and handle disparity.
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Case(self.encoder.disparity[0], {
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0b0 : self.encoder.d[0].eq(D(5, 6)), # /I1/ (Preserves disparity).
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0b1 : self.encoder.d[0].eq(D(16, 2)), # /I2/ (Flips disparity).
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}),
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NextState("START")
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)
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fsm.act("DATA",
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# Send Data.
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timer_enable.eq(1),
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sink.ready.eq(timer_done),
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If(sink.valid,
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self.encoder.d[0].eq(sink.data),
|
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).Else(
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(29, 7)), # End-of-frame /T/.
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NextState("CARRIER-EXTEND")
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)
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)
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fsm.act("CARRIER-EXTEND",
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# Extend carrier with /R/ symbols.
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self.encoder.k[0].eq(1),
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self.encoder.d[0].eq(K(23, 7)), # Carrier Extend /R/.
|
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If(parity,
|
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NextState("START")
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)
|
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)
|
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self.sync += parity.eq(~parity) # Toggle parity for /R/ extension.
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|
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# PCS RX -------------------------------------------------------------------------------------------
|
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|
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class PCSRX(LiteXModule):
|
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def __init__(self, lsb_first=False):
|
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self.rx_en = Signal()
|
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self.rx_data = Signal(8)
|
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self.sample_en = Signal()
|
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|
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self.seen_valid_ci = Signal()
|
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self.seen_config_reg = Signal()
|
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self.config_reg = Signal(16)
|
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|
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self.decoder = Decoder(lsb_first=lsb_first)
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|
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# SGMII Speed Adaptation.
|
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self.sgmii_speed = Signal(2)
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|
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# # #
|
||||
|
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# Signals.
|
||||
# --------
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count = Signal() # Byte counter for config register.
|
||||
|
||||
# SGMII Timer.
|
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# ------------
|
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timer = Signal(max=100)
|
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timer_enable = Signal()
|
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timer_done = Signal()
|
||||
self.comb += timer_done.eq(timer == 0)
|
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self.sync += [
|
||||
timer.eq(timer - 1),
|
||||
If(~timer_enable | timer_done,
|
||||
Case(self.sgmii_speed, {
|
||||
SGMII_10MBPS_SPEED : timer.eq(99),
|
||||
SGMII_100MBPS_SPEED : timer.eq( 9),
|
||||
SGMII_1000MBPS_SPEED : timer.eq( 0),
|
||||
})
|
||||
)
|
||||
]
|
||||
|
||||
# Speed adaptation
|
||||
self.comb += self.sample_en.eq(self.rx_en & timer_done)
|
||||
|
||||
# FSM.
|
||||
# ----
|
||||
self.fsm = fsm = FSM()
|
||||
fsm.act("START",
|
||||
# Wait for a K-character.
|
||||
If(self.decoder.k,
|
||||
# K-character is Config or Idle K28.5.
|
||||
If(self.decoder.d == K(28, 5),
|
||||
NextValue(count, 0),
|
||||
NextState("CONFIG-D-OR-IDLE")
|
||||
),
|
||||
# K-character is Start-of-packet /S/.
|
||||
If(self.decoder.d == K(27, 7),
|
||||
timer_enable.eq(1),
|
||||
self.rx_en.eq(1),
|
||||
self.rx_data.eq(0x55), # First Preamble Byte.
|
||||
NextState("DATA")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("CONFIG-D-OR-IDLE",
|
||||
NextState("ERROR"),
|
||||
If(~self.decoder.k,
|
||||
# Check for Configuration Word.
|
||||
If((self.decoder.d == D(21, 5)) | # /C1/.
|
||||
(self.decoder.d == D( 2, 2)), # /C2/.
|
||||
self.seen_valid_ci.eq(1),
|
||||
NextState("CONFIG-REG")
|
||||
),
|
||||
# Check for Idle Word.
|
||||
If((self.decoder.d == D( 5, 6)) | # /I1/.
|
||||
(self.decoder.d == D(16, 2)), # /I2/.
|
||||
self.seen_valid_ci.eq(1),
|
||||
NextState("START")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("CONFIG-REG",
|
||||
NextState("ERROR"),
|
||||
If(~self.decoder.k,
|
||||
# Receive for Configuration Register.
|
||||
NextState("CONFIG-REG"),
|
||||
NextValue(count, count + 1),
|
||||
Case(count, {
|
||||
0b0 : NextValue(self.config_reg[:8], self.decoder.d), # LSB.
|
||||
0b1 : NextValue(self.config_reg[8:], self.decoder.d), # MSB.
|
||||
}),
|
||||
If(count == (2 - 1),
|
||||
self.seen_config_reg.eq(1),
|
||||
NextState("START")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("DATA",
|
||||
NextState("START"),
|
||||
If(~self.decoder.k,
|
||||
# Receive Data.
|
||||
timer_enable.eq(1),
|
||||
self.rx_en.eq(1),
|
||||
self.rx_data.eq(self.decoder.d),
|
||||
NextState("DATA")
|
||||
)
|
||||
)
|
||||
fsm.act("ERROR",
|
||||
NextState("START")
|
||||
)
|
||||
|
||||
# PCS ----------------------------------------------------------------------------------------------
|
||||
|
||||
# FIXME: Needs similar cleanup than PCSTX/RX.
|
||||
|
||||
class PCS(LiteXModule):
|
||||
def __init__(self, lsb_first=False, check_period=6e-3, more_ack_time=10e-3):
|
||||
self.tx = ClockDomainsRenamer("eth_tx")(PCSTX(lsb_first=lsb_first))
|
||||
|
@ -301,18 +282,16 @@ class PCS(LiteXModule):
|
|||
|
||||
self.link_up = Signal()
|
||||
self.restart = Signal()
|
||||
self.align = Signal()
|
||||
|
||||
self.lp_abi = BusSynchronizer(16, "eth_rx", "eth_tx")
|
||||
|
||||
# # #
|
||||
|
||||
# Endpoint interface.
|
||||
self.comb += [
|
||||
self.tx.tx_valid.eq(self.sink.valid),
|
||||
self.sink.ready.eq(self.tx.tx_ready),
|
||||
self.tx.tx_data.eq(self.sink.data),
|
||||
]
|
||||
# Sink -> TX.
|
||||
self.comb += self.sink.connect(self.tx.sink, omit={"last_be", "error"})
|
||||
|
||||
# RX -> Source.
|
||||
rx_en_d = Signal()
|
||||
self.sync.eth_rx += [
|
||||
rx_en_d.eq(self.rx.rx_en),
|
||||
|
@ -321,11 +300,12 @@ class PCS(LiteXModule):
|
|||
]
|
||||
self.comb += self.source.last.eq(~self.rx.rx_en & rx_en_d)
|
||||
|
||||
# Main module.
|
||||
# Seen Valid Synchronizer.
|
||||
seen_valid_ci = PulseSynchronizer("eth_rx", "eth_tx")
|
||||
self.submodules += seen_valid_ci
|
||||
self.comb += seen_valid_ci.i.eq(self.rx.seen_valid_ci)
|
||||
|
||||
# Checker.
|
||||
checker_max_val = ceil(check_period*125e6)
|
||||
checker_counter = Signal(max=checker_max_val+1)
|
||||
checker_tick = Signal()
|
||||
|
@ -352,8 +332,8 @@ class PCS(LiteXModule):
|
|||
# Detect that link is down:
|
||||
# - 1000BASE-X : linkup can be inferred by non-empty reg.
|
||||
# - SGMII : linkup is indicated with bit 15.
|
||||
linkdown.eq((self.lp_abi.o[0] & ~self.lp_abi.o[15]) | (self.lp_abi.o == 0)),
|
||||
self.tx.sgmii_speed.eq(Mux(self.lp_abi.o[0],
|
||||
linkdown.eq((is_sgmii & ~self.lp_abi.o[15]) | (self.lp_abi.o == 0)),
|
||||
self.tx.sgmii_speed.eq(Mux(is_sgmii,
|
||||
self.lp_abi.o[10:12], 0b10)),
|
||||
self.rx.sgmii_speed.eq(Mux(self.lp_abi.i[0],
|
||||
self.lp_abi.i[10:12], 0b10))
|
||||
|
@ -363,7 +343,7 @@ class PCS(LiteXModule):
|
|||
self.tx.config_reg.eq(Mux(tx_config_empty, 0,
|
||||
(is_sgmii) | # SGMII: SGMII in-use
|
||||
(~is_sgmii << 5) | # 1000BASE-X: Full-duplex
|
||||
(Mux(self.lp_abi.o[0], # SGMII: Speed
|
||||
(Mux(is_sgmii, # SGMII: Speed
|
||||
self.lp_abi.o[10:12], 0) << 10) |
|
||||
(is_sgmii << 12) | # SGMII: Full-duplex
|
||||
(autoneg_ack << 14) | # SGMII/1000BASE-X: Acknowledge Bit
|
||||
|
@ -391,11 +371,12 @@ class PCS(LiteXModule):
|
|||
)
|
||||
# ABILITY_DETECT
|
||||
fsm.act("AUTONEG_WAIT_ABI",
|
||||
self.align.eq(1),
|
||||
self.tx.config_valid.eq(1),
|
||||
If(rx_config_reg_abi.o,
|
||||
NextState("AUTONEG_WAIT_ACK")
|
||||
),
|
||||
If(checker_tick & ~checker_ok,
|
||||
If((checker_tick & ~checker_ok) | rx_config_reg_ack.o,
|
||||
self.restart.eq(1),
|
||||
NextState("AUTONEG_BREAKLINK")
|
||||
)
|
||||
|
|
|
@ -612,7 +612,7 @@ class USP_GTH_1000BASEX(LiteXModule):
|
|||
i_RXCHBONDLEVEL = 0b000,
|
||||
i_RXCHBONDMASTER = 0b0,
|
||||
i_RXCHBONDSLAVE = 0b0,
|
||||
i_RXCOMMADETEN = 0b0,
|
||||
i_RXCOMMADETEN = 0b1,
|
||||
i_RXDFEAGCCTRL = 0b01,
|
||||
i_RXDFEAGCHOLD = 0b0,
|
||||
i_RXDFEAGCOVRDEN = 0b0,
|
||||
|
@ -668,14 +668,14 @@ class USP_GTH_1000BASEX(LiteXModule):
|
|||
i_RXLPMLFKLOVRDEN = 0b0,
|
||||
i_RXLPMOSHOLD = 0b0,
|
||||
i_RXLPMOSOVRDEN = 0b0,
|
||||
i_RXMCOMMAALIGNEN = 0b0,
|
||||
i_RXMCOMMAALIGNEN = pcs.align,
|
||||
i_RXMONITORSEL = 0b00,
|
||||
i_RXOOBRESET = 0b0,
|
||||
i_RXOSCALRESET = 0b0,
|
||||
i_RXOSHOLD = 0b0,
|
||||
i_RXOSOVRDEN = 0b0,
|
||||
i_RXOUTCLKSEL = 0b101,
|
||||
i_RXPCOMMAALIGNEN = 0b0,
|
||||
i_RXPCOMMAALIGNEN = pcs.align,
|
||||
i_RXPCSRESET = 0b0,
|
||||
i_RXPD = 0b00,
|
||||
i_RXPHALIGNEN = 0b0,
|
||||
|
|
|
@ -641,7 +641,7 @@ class USP_GTY_1000BASEX(LiteXModule):
|
|||
i_RXCHBONDSLAVE = 0b0,
|
||||
i_RXCKCALRESET = 0b0,
|
||||
i_RXCKCALSTART = 0b0,
|
||||
i_RXCOMMADETEN = 0b0,
|
||||
i_RXCOMMADETEN = 0b1,
|
||||
i_RXDFEAGCHOLD = 0b0,
|
||||
i_RXDFEAGCOVRDEN = 0b0,
|
||||
i_RXDFECFOKFCNUM = 0b0,
|
||||
|
@ -704,14 +704,14 @@ class USP_GTY_1000BASEX(LiteXModule):
|
|||
i_RXLPMLFKLOVRDEN = 0b0,
|
||||
i_RXLPMOSHOLD = 0b0,
|
||||
i_RXLPMOSOVRDEN = 0b0,
|
||||
i_RXMCOMMAALIGNEN = 0b0,
|
||||
i_RXMCOMMAALIGNEN = pcs.align,
|
||||
i_RXMONITORSEL = 0b00,
|
||||
i_RXOOBRESET = 0b0,
|
||||
i_RXOSCALRESET = 0b0,
|
||||
i_RXOSHOLD = 0b0,
|
||||
i_RXOSOVRDEN = 0b0,
|
||||
i_RXOUTCLKSEL = 0b101,
|
||||
i_RXPCOMMAALIGNEN = 0b0,
|
||||
i_RXPCOMMAALIGNEN = pcs.align,
|
||||
i_RXPCSRESET = 0b0,
|
||||
i_RXPD = 0b00,
|
||||
i_RXPHALIGN = 0b0,
|
||||
|
|
|
@ -479,9 +479,9 @@ class V7_1000BASEX(LiteXModule):
|
|||
o_RXBYTEISALIGNED = Open(),
|
||||
o_RXBYTEREALIGN = Open(),
|
||||
o_RXCOMMADET = Open(),
|
||||
i_RXCOMMADETEN = 1,
|
||||
i_RXMCOMMAALIGNEN = 1,
|
||||
i_RXPCOMMAALIGNEN = 1,
|
||||
i_RXCOMMADETEN = 0b1,
|
||||
i_RXMCOMMAALIGNEN = pcs.align,
|
||||
i_RXPCOMMAALIGNEN = pcs.align,
|
||||
|
||||
# Receive Ports - RX Channel Bonding Ports
|
||||
o_RXCHANBONDSEQ = Open(),
|
||||
|
|
Loading…
Reference in New Issue