154 lines
5.7 KiB
Python
154 lines
5.7 KiB
Python
from migen.bus import wishbone
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from migen.genlib.io import CRG
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from migen.fhdl.specials import Keep
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from misoclib.soc import SoC
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from misoclib.com.uart.bridge import UARTWishboneBridge
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from liteeth.common import *
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from liteeth.phy import LiteEthPHY
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from liteeth.core import LiteEthUDPIPCore
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class BaseSoC(SoC):
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csr_map = {
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"phy": 11,
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"core": 12
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform, clk_freq=166*1000000,
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mac_address=0x10e2d5000000,
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ip_address="192.168.0.42"):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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# wishbone SRAM (to test Wishbone over UART and Etherbone)
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self.submodules.sram = wishbone.SRAM(1024)
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self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
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# ethernet PHY and UDP/IP stack
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self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq)
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self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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self.specials += [
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Keep(self.crg.cd_sys.clk),
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Keep(self.phy.crg.cd_eth_rx.clk),
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Keep(self.phy.crg.cd_eth_tx.clk)
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]
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platform.add_platform_command("""
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create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
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create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
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create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
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set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
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set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
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""")
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class BaseSoCDevel(BaseSoC):
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csr_map = {
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"logic_analyzer": 20
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform):
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from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
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from litescope.core.port import LiteScopeTerm
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BaseSoC.__init__(self, platform)
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self.core_icmp_rx_fsm_state = Signal(4)
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self.core_icmp_tx_fsm_state = Signal(4)
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self.core_udp_rx_fsm_state = Signal(4)
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self.core_udp_tx_fsm_state = Signal(4)
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self.core_ip_rx_fsm_state = Signal(4)
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self.core_ip_tx_fsm_state = Signal(4)
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self.core_arp_rx_fsm_state = Signal(4)
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self.core_arp_tx_fsm_state = Signal(4)
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self.core_arp_table_fsm_state = Signal(4)
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debug = (
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# MAC interface
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self.core.mac.core.sink.stb,
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self.core.mac.core.sink.sop,
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self.core.mac.core.sink.eop,
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self.core.mac.core.sink.ack,
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self.core.mac.core.sink.data,
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self.core.mac.core.source.stb,
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self.core.mac.core.source.sop,
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self.core.mac.core.source.eop,
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self.core.mac.core.source.ack,
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self.core.mac.core.source.data,
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# ICMP interface
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self.core.icmp.echo.sink.stb,
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self.core.icmp.echo.sink.sop,
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self.core.icmp.echo.sink.eop,
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self.core.icmp.echo.sink.ack,
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self.core.icmp.echo.sink.data,
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self.core.icmp.echo.source.stb,
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self.core.icmp.echo.source.sop,
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self.core.icmp.echo.source.eop,
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self.core.icmp.echo.source.ack,
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self.core.icmp.echo.source.data,
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# IP interface
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self.core.ip.crossbar.master.sink.stb,
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self.core.ip.crossbar.master.sink.sop,
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self.core.ip.crossbar.master.sink.eop,
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self.core.ip.crossbar.master.sink.ack,
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self.core.ip.crossbar.master.sink.data,
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self.core.ip.crossbar.master.sink.ip_address,
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self.core.ip.crossbar.master.sink.protocol,
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# State machines
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self.core_icmp_rx_fsm_state,
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self.core_icmp_tx_fsm_state,
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self.core_arp_rx_fsm_state,
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self.core_arp_tx_fsm_state,
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self.core_arp_table_fsm_state,
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self.core_ip_rx_fsm_state,
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self.core_ip_tx_fsm_state,
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self.core_udp_rx_fsm_state,
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self.core_udp_tx_fsm_state
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)
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self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(debug, 4096)
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self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
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def do_finalize(self):
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BaseSoC.do_finalize(self)
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self.comb += [
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self.core_icmp_rx_fsm_state.eq(self.core.icmp.rx.fsm.state),
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self.core_icmp_tx_fsm_state.eq(self.core.icmp.tx.fsm.state),
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self.core_arp_rx_fsm_state.eq(self.core.arp.rx.fsm.state),
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self.core_arp_tx_fsm_state.eq(self.core.arp.tx.fsm.state),
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self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state),
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self.core_ip_rx_fsm_state.eq(self.core.ip.rx.fsm.state),
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self.core_ip_tx_fsm_state.eq(self.core.ip.tx.fsm.state),
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self.core_udp_rx_fsm_state.eq(self.core.udp.rx.fsm.state),
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self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state)
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]
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def do_exit(self, vns):
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self.logic_analyzer.export(vns, "test/logic_analyzer.csv")
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default_subtarget = BaseSoC
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