mirror of
https://github.com/enjoy-digital/liteeth.git
synced 2025-01-03 03:43:37 -05:00
108 lines
3.4 KiB
Python
108 lines
3.4 KiB
Python
from liteeth.common import *
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def converter_description(dw):
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payload_layout = [("data", dw)]
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return EndpointDescription(payload_layout, packetized=True)
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@CEInserter()
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class LiteEthPHYRMIITX(Module):
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def __init__(self, pads):
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self.sink = sink = Sink(eth_phy_description(8))
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# # #
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converter = Converter(converter_description(8),
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converter_description(2))
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(sink.stb),
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converter.sink.data.eq(sink.data),
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sink.ack.eq(converter.sink.ack),
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converter.source.ack.eq(1)
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]
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self.sync += [
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pads.tx_en.eq(converter.source.stb),
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pads.tx_data.eq(converter.source.data)
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]
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@CEInserter()
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class LiteEthPHYRMIIRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_phy_description(8))
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# # #
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sop = Signal(reset=1)
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sop_set = Signal()
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sop_clr = Signal()
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self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0))
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converter = Converter(converter_description(2),
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converter_description(8))
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converter = ResetInserter()(converter)
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self.submodules += converter
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self.sync += [
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converter.reset.eq(~pads.dv),
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converter.sink.stb.eq(1),
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converter.sink.data.eq(pads.rx_data)
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]
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self.sync += [
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sop_set.eq(~pads.dv),
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sop_clr.eq(pads.dv)
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]
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self.comb += [
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converter.sink.sop.eq(sop),
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converter.sink.eop.eq(~pads.dv)
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]
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self.comb += Record.connect(converter.source, source)
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class LiteEthPHYMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset):
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self._reset = CSRStorage()
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self.ref_clk = Signal()
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# # #
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# assumming 100MHz clock provided externally
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self.sync.eth += self.ref_clk.eq(~self.ref_clk)
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self.comb += clock_pads.ref_clk.eq(self.ref_clk)
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += self.cd_eth_rx.clk.eq(ClockSignal("eth"))
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self.comb += self.cd_eth_tx.clk.eq(ClockSignal("eth"))
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if with_hw_init_reset:
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reset = Signal()
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counter_done = Signal()
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self.submodules.counter = counter = Counter(max=512)
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self.comb += [
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counter_done.eq(counter.value == 256),
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counter.ce.eq(~counter_done),
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reset.eq(~counter_done | self._reset.storage)
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]
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else:
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reset = self._reset.storage
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYRMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIIRX(pads))
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self.comb += [
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self.tx.ce.eq(self.crg.ref_clk == 1),
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self.rx.ce.eq(self.crg.ref_clk == 1)
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]
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self.sink, self.source = self.tx.sink, self.rx.source
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