enjoy-digital 97dccdb294 Merge pull request #124 from sensille/wishbone_rx ... wishbone rx data corruption		2022-12-20 09:53:34 +01:00
..
core	liteeth/core: Expose IP broadcast capability.	2022-06-27 15:46:23 +02:00
frontend	frontend/stream: Add packet support and remove send_level.	2022-07-29 14:58:25 +02:00
mac	mac: fix typo	2022-12-08 18:11:01 +01:00
phy	phy/k7_1000basex: Make CSR optional and allow external reset control.	2022-11-04 12:11:51 +01:00
software	software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).	2020-11-24 19:40:18 +01:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	frontend/stream: Add packet support and remove send_level.	2022-07-29 14:58:25 +02:00
crossbar.py	crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design.	2022-01-26 10:51:07 +01:00
gen.py	liteth_gen: eth_bus_standard -> bus_standard.	2022-11-21 12:13:57 +01:00
packet.py	packet.py: fix typo in Packetizer	2022-04-19 01:15:10 +02:00