mirror of
https://github.com/enjoy-digital/liteeth.git
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90 lines
3.1 KiB
Python
90 lines
3.1 KiB
Python
from liteeth.common import *
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from litex.gen.genlib.io import DDROutput
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from litex.gen.genlib.resetsync import AsyncResetSynchronizer
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from liteeth.phy.common import *
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class LiteEthPHYGMIITX(Module):
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def __init__(self, pads):
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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# # #
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if hasattr(pads, "tx_er"):
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pads.tx_er.reset_less = True
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self.sync += pads.tx_er.eq(0)
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pads.tx_en.reset_less = True
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pads.tx_data.reset_less = True
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self.sync += [
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pads.tx_en.eq(sink.valid),
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pads.tx_data.eq(sink.data),
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sink.ready.eq(1)
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]
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class LiteEthPHYGMIIRX(Module):
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def __init__(self, pads):
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self.source = source = stream.Endpoint(eth_phy_description(8))
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# # #
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dv_d = Signal()
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self.sync += [
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dv_d.eq(pads.dv),
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source.valid.eq(pads.dv),
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source.data.eq(pads.rx_data)
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]
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self.comb += source.last.eq(~pads.dv & dv_d)
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class LiteEthPHYGMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
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self._reset = CSRStorage()
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# # #
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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# RX : Let the synthesis tool insert the appropriate clock buffer
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self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
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# TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
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# MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
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self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
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if isinstance(mii_mode, int) and (mii_mode == 0):
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self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
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else:
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# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
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self.specials += Instance("BUFGMUX",
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i_I0=self.cd_eth_rx.clk,
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i_I1=clock_pads.tx,
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i_S=mii_mode,
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o_O=self.cd_eth_tx.clk)
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reset = Signal()
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if with_hw_init_reset:
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self.submodules.hw_reset = LiteEthPHYHWReset()
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self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
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else:
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self.comb += reset.eq(self._reset.storage)
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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if hasattr(pads, "mdc"):
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self.submodules.mdio = LiteEthPHYMDIO(pads)
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