150 lines
4.5 KiB
Python
150 lines
4.5 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.core.mac import LiteEthMAC
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from misoclib.com.liteeth.test.common import *
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from misoclib.com.liteeth.test.model import phy, mac
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class WishboneMaster:
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def __init__(self, obj):
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self.obj = obj
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self.dat = 0
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def write(self, adr, dat):
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self.obj.cyc = 1
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self.obj.stb = 1
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self.obj.adr = adr
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self.obj.we = 1
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self.obj.sel = 0xF
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self.obj.dat_w = dat
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while self.obj.ack == 0:
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yield
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self.obj.cyc = 0
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self.obj.stb = 0
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yield
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def read(self, adr):
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self.obj.cyc = 1
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self.obj.stb = 1
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self.obj.adr = adr
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self.obj.we = 0
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self.obj.sel = 0xF
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self.obj.dat_w = 0
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while self.obj.ack == 0:
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yield
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self.dat = self.obj.dat_r
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self.obj.cyc = 0
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self.obj.stb = 0
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yield
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class SRAMReaderDriver:
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def __init__(self, obj):
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self.obj = obj
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def start(self, slot, length):
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self.obj._slot.storage = slot
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self.obj._length.storage = length
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self.obj._start.re = 1
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yield
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self.obj._start.re = 0
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yield
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def wait_done(self):
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while self.obj.ev.done.pending == 0:
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yield
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def clear_done(self):
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self.obj.ev.done.clear = 1
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yield
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self.obj.ev.done.clear = 0
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yield
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class SRAMWriterDriver:
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def __init__(self, obj):
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self.obj = obj
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def wait_available(self):
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while self.obj.ev.available.pending == 0:
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yield
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def clear_available(self):
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self.obj.ev.available.clear = 1
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yield
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self.obj.ev.available.clear = 0
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yield
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
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self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_preamble_crc=True)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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wishbone_master = WishboneMaster(selfp.ethmac.bus)
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sram_reader_driver = SRAMReaderDriver(selfp.ethmac.interface.sram.reader)
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sram_writer_driver = SRAMWriterDriver(selfp.ethmac.interface.sram.writer)
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sram_writer_slots_offset = [0x000, 0x200]
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sram_reader_slots_offset = [0x400, 0x600]
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length = 150+2
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tx_payload = [seed_to_data(i, True) % 0xFF for i in range(length)] + [0, 0, 0, 0]
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errors = 0
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while True:
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for slot in range(2):
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print("slot {}: ".format(slot), end="")
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# fill tx memory
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for i in range(length//4+1):
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
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# send tx payload & wait
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yield from sram_reader_driver.start(slot, length)
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yield from sram_reader_driver.wait_done()
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yield from sram_reader_driver.clear_done()
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# wait rx
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yield from sram_writer_driver.wait_available()
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yield from sram_writer_driver.clear_available()
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# get rx payload (loopback on PHY Model)
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rx_payload = []
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for i in range(length//4+1):
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yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
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dat = wishbone_master.dat
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rx_payload += list(dat.to_bytes(4, byteorder='big'))
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# check results
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s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=3000, vcd_name="my.vcd", keep_files=True)
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