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liteeth
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liteeth
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liteeth
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Florent Kermarrec
dd1988a40d
frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastHandler for 64-bit case.
2024-09-20 12:15:18 +02:00
..
core
core: Expose icmp_fifo_depth paramter.
2024-09-19 22:18:53 +02:00
frontend
frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastHandler for 64-bit case.
2024-09-20 12:15:18 +02:00
mac
mac: Move LiteEthMACLastBE module to common.py and rename to LiteEthLastHandler.
2024-09-12 13:32:38 +02:00
phy
Merge branch 'enjoy-digital:master' into master
2024-09-17 16:56:26 -03:00
software
software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).
2020-11-24 19:40:18 +01:00
__init__.py
init repo
2015-09-07 13:29:34 +02:00
common.py
core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth.
2023-07-10 11:13:52 +02:00
crossbar.py
crossbar: Switch to LiteXModule.
2023-07-10 09:53:45 +02:00
gen.py
liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated externally).
2024-09-11 15:21:24 +02:00
packet.py
packet: Switch to LiteX/Module.
2023-07-10 10:24:37 +02:00