Fin Maaß 3693c61cbe phy/rmii: fix it for efinix ... On efinix platforms the clk signal of `SDROutput` and `SDRInput` has to come from the PLL. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>		2024-09-25 17:06:29 +02:00
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core	liteeth/core/__init__.py: Switch to LiteXModule.	2024-09-20 16:19:03 +02:00
frontend	frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastHandler for 64-bit case.	2024-09-20 12:15:18 +02:00
mac	liteeth/mac/core: Allow PHY to enforce with_preamble_crc/with_padding parameters.	2024-09-23 16:35:28 +02:00
phy	phy/rmii: fix it for efinix	2024-09-25 17:06:29 +02:00
software	software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).	2020-11-24 19:40:18 +01:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth.	2023-07-10 11:13:52 +02:00
crossbar.py	crossbar: Switch to LiteXModule.	2023-07-10 09:53:45 +02:00
gen.py	liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated externally).	2024-09-11 15:21:24 +02:00
packet.py	packet: Switch to LiteX/Module.	2023-07-10 10:24:37 +02:00