282 lines
9.0 KiB
Python
282 lines
9.0 KiB
Python
#!/usr/bin/env python3
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import argparse
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.platform import XilinxPlatform
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.common import *
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.phy.rmii import LiteEthPHYRMII
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from liteeth.phy.gmii import LiteEthPHYGMII
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from liteeth.core.mac import LiteEthMAC
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from liteeth.core import LiteEthUDPIPCore
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_io = [
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("sys_clock", 0, Pins(1)),
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("sys_reset", 1, Pins(1)),
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# MII PHY Pads
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("mii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("mii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("dv", Pins(1)),
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Subsignal("rx_er", Pins(1)),
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Subsignal("rx_data", Pins(4)),
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Subsignal("tx_en", Pins(4)),
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Subsignal("tx_data", Pins(4)),
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Subsignal("col", Pins(1)),
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Subsignal("crs", Pins(1))
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),
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# RMII PHY Pads
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("rmii_eth_clocks", 0,
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Subsignal("ref_clk", Pins(1))
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),
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("rmii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("rx_data", Pins(2)),
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Subsignal("crs_dv", Pins(1)),
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Subsignal("tx_en", Pins(1)),
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Subsignal("tx_data", Pins(2)),
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Subsignal("mdc", Pins(1)),
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Subsignal("mdio", Pins(1)),
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),
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# GMII PHY Pads
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("gmii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("gtx", Pins(1)),
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Subsignal("rx", Pins(1))
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),
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("gmii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("int_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("dv", Pins(1)),
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Subsignal("rx_er", Pins(1)),
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Subsignal("rx_data", Pins(8)),
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Subsignal("tx_en", Pins(1)),
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Subsignal("tx_er", Pins(1)),
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Subsignal("tx_data", Pins(8)),
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Subsignal("col", Pins(1)),
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Subsignal("crs", Pins(1))
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),
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# RGMII PHY Pads
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("rgmii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1))
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),
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("rgmii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("int_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("rx_ctl", Pins(1)),
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Subsignal("rx_data", Pins(4)),
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Subsignal("tx_ctl", Pins(1)),
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Subsignal("tx_data", Pins(4))
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),
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# Wishbone
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("wishbone", 0,
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Subsignal("adr", Pins(30)),
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Subsignal("dat_r", Pins(32)),
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Subsignal("dat_w", Pins(32)),
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Subsignal("sel", Pins(4)),
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Subsignal("cyc", Pins(1)),
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Subsignal("stb", Pins(1)),
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Subsignal("ack", Pins(1)),
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Subsignal("we", Pins(1)),
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Subsignal("cti", Pins(3)),
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Subsignal("bte", Pins(2)),
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Subsignal("err", Pins(1))
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),
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# UDP
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("udp_sink", 0,
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Subsignal("valid", Pins(1)),
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Subsignal("last", Pins(1)),
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Subsignal("ready", Pins(1)),
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# param
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Subsignal("src_port", Pins(16)),
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Subsignal("dst_port", Pins(16)),
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Subsignal("ip_address", Pins(32)),
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Subsignal("length", Pins(16)),
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# payload
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Subsignal("data", Pins(32)),
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Subsignal("error", Pins(4))
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),
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("udp_source", 0,
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Subsignal("valid", Pins(1)),
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Subsignal("last", Pins(1)),
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Subsignal("ready", Pins(1)),
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# param
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Subsignal("src_port", Pins(16)),
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Subsignal("dst_port", Pins(16)),
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Subsignal("ip_address", Pins(32)),
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Subsignal("length", Pins(16)),
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# payload
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Subsignal("data", Pins(32)),
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Subsignal("error", Pins(4))
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),
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]
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class CorePlatform(XilinxPlatform):
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name = "core"
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7", _io)
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def do_finalize(self, *args, **kwargs):
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pass
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class PHYCore(SoCCore):
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def __init__(self, phy, clk_freq):
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platform = CorePlatform()
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SoCCore.__init__(self, platform,
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clk_freq=clk_freq,
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cpu_type=None,
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integrated_rom_size=0x0,
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integrated_sram_size=0x0,
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integrated_main_ram_size=0x0,
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csr_address_width=14, csr_data_width=8,
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with_uart=False, with_timer=False)
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self.submodules.crg = CRG(platform.request("sys_clock"),
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platform.request("sys_reset"))
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# ethernet
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if phy == "MII":
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self.submodules.ethphy = LiteEthPHYMII(platform.request("mii_eth_clocks"),
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platform.request("mii_eth"))
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elif phy == "RMII":
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self.submodules.ethphy = LiteEthPHYRMII(platform.request("rmii_eth_clocks"),
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platform.request("rmii_eth"))
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elif phy == "GMII":
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self.submodules.ethphy = LiteEthPHYGMII(platform.request("gmii_eth_clocks"),
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platform.request("gmii_eth"))
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elif phy == "RGMII":
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self.submodules.ethphy = LiteEthPHYRGMII(platform.request("rgmii_eth_clocks"),
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platform.request("rgmii_eth"))
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else:
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ValueError("Unsupported " + phy + " PHY");
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class MACCore(PHYCore):
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csr_peripherals = (
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"ethphy",
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"ethmac"
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)
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csr_map = dict((n, v) for v, n in enumerate(csr_peripherals, start=16))
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csr_map.update(SoCCore.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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mem_map = {
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"ethmac": 0x50000000
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, phy, clk_freq):
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PHYCore.__init__(self, phy, clk_freq)
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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class _WishboneBridge(Module):
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def __init__(self, interface):
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self.wishbone = interface
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self.add_cpu_or_bridge(_WishboneBridge(self.platform.request("wishbone")))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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class UDPCore(PHYCore):
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def __init__(self, phy, clk_freq, mac_address, ip_address, port):
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PHYCore.__init__(self, phy, clk_freq)
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self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq)
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udp_port = self.core.udp.crossbar.get_port(port, 8)
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# XXX avoid manual connect
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udp_sink = self.platform.request("udp_sink")
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self.comb += [
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# control
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udp_port.sink.valid.eq(udp_sink.valid),
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udp_port.sink.last.eq(udp_sink.last),
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udp_sink.ready.eq(udp_port.sink.ready),
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# param
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udp_port.sink.src_port.eq(udp_sink.src_port),
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udp_port.sink.dst_port.eq(udp_sink.dst_port),
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udp_port.sink.ip_address.eq(udp_sink.ip_address),
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udp_port.sink.length.eq(udp_sink.length),
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# payload
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udp_port.sink.data.eq(udp_sink.data),
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udp_port.sink.error.eq(udp_sink.error)
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]
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udp_source = self.platform.request("udp_source")
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self.comb += [
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# control
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udp_source.valid.eq(udp_port.source.valid),
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udp_source.last.eq(udp_port.source.last),
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udp_port.source.ready.eq(udp_source.ready),
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# param
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udp_source.src_port.eq(udp_port.source.src_port),
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udp_source.dst_port.eq(udp_port.source.dst_port),
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udp_source.ip_address.eq(udp_port.source.ip_address),
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udp_source.length.eq(udp_port.source.length),
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# payload
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udp_source.data.eq(udp_port.source.data),
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udp_source.error.eq(udp_port.source.error)
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]
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def main():
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parser = argparse.ArgumentParser(description="LiteEth core builder")
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--phy", default="MII", help="Ethernet PHY(MII/RMII/GMII/RMGII)")
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parser.add_argument("--core", default="wishbone", help="Ethernet Core(wishbone/udp)")
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parser.add_argument("--mac_address", default=0x10e2d5000000, help="MAC address")
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parser.add_argument("--ip_address", default="192.168.1.50", help="IP address")
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args = parser.parse_args()
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if args.core == "mac":
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soc = MACCore(phy=args.phy, clk_freq=100*1000000)
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elif args.core == "udp":
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soc = UDPCore(phy=args.phy, clk_freq=100*10000000,
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mac_address=args.mac_address,
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ip_address=args.ip_address,
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port=6000)
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else:
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raise ValueError
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builder = Builder(soc, output_dir="liteeth", compile_gateware=False, csr_csv="liteeth/csr.csv")
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builder.build(build_name="liteeth")
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if __name__ == "__main__":
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main()
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