mirror of
https://github.com/enjoy-digital/liteeth.git
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302 lines
11 KiB
Python
302 lines
11 KiB
Python
#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from liteeth.common import *
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from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect.packet import Depacketizer, Packetizer
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# ARP Layouts --------------------------------------------------------------------------------------
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_arp_table_layout = [
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("reply", 1),
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("request", 1),
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("ip_address", 32),
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("mac_address", 48)
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]
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# ARP TX -------------------------------------------------------------------------------------------
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class LiteEthARPPacketizer(Packetizer):
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def __init__(self, dw=8):
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Packetizer.__init__(self,
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eth_arp_description(dw),
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eth_mac_description(dw),
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arp_header)
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class LiteEthARPTX(Module):
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def __init__(self, mac_address, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(_arp_table_layout)
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self.source = source = stream.Endpoint(eth_mac_description(dw))
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# # #
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counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True)
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self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ready.eq(1),
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NextValue(counter, 0),
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If(sink.valid,
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sink.ready.eq(0),
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NextState("SEND")
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)
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)
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self.comb += [
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packetizer.sink.last.eq(counter == max(arp_header.length, eth_min_len)-1),
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packetizer.sink.hwtype.eq(arp_hwtype_ethernet),
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packetizer.sink.proto.eq(arp_proto_ip),
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packetizer.sink.hwsize.eq(6),
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packetizer.sink.protosize.eq(4),
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packetizer.sink.sender_mac.eq(mac_address),
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packetizer.sink.sender_ip.eq(ip_address),
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If(sink.reply,
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packetizer.sink.opcode.eq(arp_opcode_reply),
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packetizer.sink.target_mac.eq(sink.mac_address),
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packetizer.sink.target_ip.eq(sink.ip_address)
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).Elif(sink.request,
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packetizer.sink.opcode.eq(arp_opcode_request),
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packetizer.sink.target_mac.eq(0xffffffffffff),
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packetizer.sink.target_ip.eq(sink.ip_address)
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)
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]
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fsm.act("SEND",
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packetizer.sink.valid.eq(1),
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packetizer.source.connect(source),
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source.target_mac.eq(packetizer.sink.target_mac),
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source.sender_mac.eq(mac_address),
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source.ethernet_type.eq(ethernet_type_arp),
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If(source.valid & source.ready,
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NextValue(counter, counter + 1),
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If(source.last,
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sink.ready.eq(1),
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NextState("IDLE")
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)
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)
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)
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# ARP RX -------------------------------------------------------------------------------------------
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class LiteEthARPDepacketizer(Depacketizer):
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def __init__(self, dw=8):
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Depacketizer.__init__(self,
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eth_mac_description(dw),
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eth_arp_description(dw),
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arp_header)
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class LiteEthARPRX(Module):
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def __init__(self, mac_address, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_mac_description(dw))
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self.source = source = stream.Endpoint(_arp_table_layout)
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# # #s
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self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer(dw)
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self.comb += sink.connect(depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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depacketizer.source.ready.eq(1),
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If(depacketizer.source.valid,
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depacketizer.source.ready.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal(reset_less=True)
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self.sync += valid.eq(
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depacketizer.source.valid &
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(depacketizer.source.hwtype == arp_hwtype_ethernet) &
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(depacketizer.source.proto == arp_proto_ip) &
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(depacketizer.source.hwsize == 6) &
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(depacketizer.source.protosize == 4) &
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(depacketizer.source.target_ip == ip_address)
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)
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reply = Signal()
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request = Signal()
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self.comb += Case(depacketizer.source.opcode, {
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arp_opcode_request: [request.eq(1)],
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arp_opcode_reply: [reply.eq(1)],
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"default": []
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})
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self.comb += [
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source.ip_address.eq(depacketizer.source.sender_ip),
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source.mac_address.eq(depacketizer.source.sender_mac)
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]
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fsm.act("CHECK",
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If(valid,
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source.valid.eq(1),
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source.reply.eq(reply),
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source.request.eq(request)
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),
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NextState("TERMINATE")
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),
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fsm.act("TERMINATE",
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depacketizer.source.ready.eq(1),
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If(depacketizer.source.valid & depacketizer.source.last,
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NextState("IDLE")
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)
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)
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# ARP Table ----------------------------------------------------------------------------------------
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class LiteEthARPTable(Module):
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def __init__(self, clk_freq, max_requests=8):
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self.sink = sink = stream.Endpoint(_arp_table_layout) # from arp_rx
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self.source = source = stream.Endpoint(_arp_table_layout) # to arp_tx
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# Request/Response interface
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self.request = request = stream.Endpoint(arp_table_request_layout)
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self.response = response = stream.Endpoint(arp_table_response_layout)
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# # #
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request_pending = Signal()
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request_pending_clr = Signal()
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request_pending_set = Signal()
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self.sync += \
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If(request_pending_clr,
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request_pending.eq(0)
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).Elif(request_pending_set,
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request_pending.eq(1)
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)
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request_ip_address = Signal(32, reset_less=True)
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request_ip_address_reset = Signal()
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request_ip_address_update = Signal()
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self.sync += \
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If(request_ip_address_reset,
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request_ip_address.eq(0)
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).Elif(request_ip_address_update,
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request_ip_address.eq(request.ip_address)
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)
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request_timer = WaitTimer(clk_freq//10)
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self.submodules += request_timer
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request_counter = Signal(max=max_requests)
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request_counter_reset = Signal()
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request_counter_ce = Signal()
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self.sync += \
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If(request_counter_reset,
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request_counter.eq(0)
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).Elif(request_counter_ce,
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request_counter.eq(request_counter + 1)
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)
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self.comb += request_timer.wait.eq(request_pending & ~request_counter_ce)
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# Note: Store only 1 IP/MAC couple, can be improved with a real
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# table in the future to improve performance when packets are
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# targeting multiple destinations.
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update = Signal()
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cached_valid = Signal()
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cached_ip_address = Signal(32, reset_less=True)
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cached_mac_address = Signal(48, reset_less=True)
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cached_timer = WaitTimer(clk_freq*10)
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self.submodules += cached_timer
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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# Note: for simplicicy, if ARP table is busy response from arp_rx
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# is lost. This is compensated by the protocol (retries)
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If(sink.valid & sink.request,
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NextState("SEND_REPLY")
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).Elif(sink.valid & sink.reply & request_pending,
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NextState("UPDATE_TABLE"),
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).Elif(request_counter == max_requests-1,
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NextState("PRESENT_RESPONSE")
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).Elif(request.valid | (request_pending & request_timer.done),
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NextState("CHECK_TABLE")
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)
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)
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fsm.act("SEND_REPLY",
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source.valid.eq(1),
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source.reply.eq(1),
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source.ip_address.eq(sink.ip_address),
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source.mac_address.eq(sink.mac_address),
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If(source.ready,
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NextState("IDLE")
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)
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)
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fsm.act("UPDATE_TABLE",
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request_pending_clr.eq(1),
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update.eq(1),
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NextState("CHECK_TABLE")
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)
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self.sync += \
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If(update,
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cached_valid.eq(1),
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cached_ip_address.eq(sink.ip_address),
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cached_mac_address.eq(sink.mac_address),
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).Else(
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If(cached_timer.done,
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cached_valid.eq(0)
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)
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)
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self.comb += cached_timer.wait.eq(~update)
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fsm.act("CHECK_TABLE",
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If(cached_valid,
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If(request_ip_address == cached_ip_address,
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request_ip_address_reset.eq(1),
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NextState("PRESENT_RESPONSE"),
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).Elif(request.ip_address == cached_ip_address,
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request.ready.eq(request.valid),
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NextState("PRESENT_RESPONSE"),
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).Else(
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request_ip_address_update.eq(request.valid),
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NextState("SEND_REQUEST")
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)
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).Else(
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request_ip_address_update.eq(request.valid),
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NextState("SEND_REQUEST")
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)
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)
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fsm.act("SEND_REQUEST",
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source.valid.eq(1),
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source.request.eq(1),
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source.ip_address.eq(request_ip_address),
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If(source.ready,
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request_counter_reset.eq(request.valid),
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request_counter_ce.eq(1),
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request_pending_set.eq(1),
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request.ready.eq(1),
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NextState("IDLE")
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)
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)
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self.comb += [
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If(request_counter == max_requests - 1,
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response.failed.eq(1),
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request_counter_reset.eq(1),
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request_pending_clr.eq(1)
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),
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response.mac_address.eq(cached_mac_address)
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]
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fsm.act("PRESENT_RESPONSE",
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response.valid.eq(1),
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If(response.ready,
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NextState("IDLE")
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)
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)
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# ARP ----------------------------------------------------------------------------------------------
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class LiteEthARP(Module):
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def __init__(self, mac, mac_address, ip_address, clk_freq, dw=8):
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self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address, dw)
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self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address, dw)
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self.submodules.table = table = LiteEthARPTable(clk_freq)
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self.comb += [
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rx.source.connect(table.sink),
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table.source.connect(tx.sink)
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]
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mac_port = mac.crossbar.get_port(ethernet_type_arp, dw=dw)
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self.comb += [
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tx.source.connect(mac_port.sink),
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mac_port.source.connect(rx.sink)
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]
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