60 lines
2.0 KiB
Python
60 lines
2.0 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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from liteeth.common import *
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from liteeth.core import LiteEthIPCore
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from liteeth.test.common import *
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from liteeth.test.model.dumps import *
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from liteeth.test.model.mac import *
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from liteeth.test.model.ip import *
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from liteeth.test.model.icmp import *
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from liteeth.test.model import phy, mac, arp, ip, icmp
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=True)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
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self.submodules.icmp_model = icmp.ICMP(self.ip_model, ip_address, debug=True)
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self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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packet = MACPacket(ping_request)
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packet.decode_remove_header()
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packet = IPPacket(packet)
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packet.decode()
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packet = ICMPPacket(packet)
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packet.decode()
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self.icmp_model.send(packet)
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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