enjoy-digital 5bc0ec00be Merge pull request #169 from VOGL-electronic/fix_phy_rmii_efinix ... phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput		2024-09-17 21:20:30 +02:00
..
core	core/ip/LiteEthIPTX: Enable buffer to ease timings on checksum.	2024-04-04 17:58:30 +02:00
frontend	frontend/stream: Add 64-bit data_width support.	2024-09-12 18:46:11 +02:00
mac	mac: Move LiteEthMACLastBE module to common.py and rename to LiteEthLastHandler.	2024-09-12 13:32:38 +02:00
phy	Merge pull request #169 from VOGL-electronic/fix_phy_rmii_efinix	2024-09-17 21:20:30 +02:00
software	software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).	2020-11-24 19:40:18 +01:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth.	2023-07-10 11:13:52 +02:00
crossbar.py	crossbar: Switch to LiteXModule.	2023-07-10 09:53:45 +02:00
gen.py	liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated externally).	2024-09-11 15:21:24 +02:00
packet.py	packet: Switch to LiteX/Module.	2023-07-10 10:24:37 +02:00