Florent Kermarrec 5c806c150e core/LiteEthUDP/IPCore: Use buffered TX/RX CDC as default since improving timing on low-end FPGAs and not impacting much resources.		2023-07-06 19:24:12 +02:00
..
core	core/LiteEthUDP/IPCore: Use buffered TX/RX CDC as default since improving timing on low-end FPGAs and not impacting much resources.	2023-07-06 19:24:12 +02:00
frontend	frontend/stream: Add 16-bit data-width support.	2023-06-28 11:02:37 +02:00
mac	liteeth: Review TX/RX CDC changes (cosmetic cleanups).	2023-07-03 19:04:58 +02:00
phy	phy/ecp5rgmii: Review/cleanup tx_clk addition.	2023-07-03 19:10:42 +02:00
software	software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).	2020-11-24 19:40:18 +01:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	frontend/stream: Add packet support and remove send_level.	2022-07-29 14:58:25 +02:00
crossbar.py	crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design.	2022-01-26 10:51:07 +01:00
gen.py	liteeth_gen: Switch to LiteXModule and remove old TODO.	2023-07-03 19:15:12 +02:00
packet.py	packet.py: fix typo in Packetizer	2022-04-19 01:15:10 +02:00