116 lines
4.3 KiB
Python
116 lines
4.3 KiB
Python
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.io import CRG
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from litex.build.xilinx.vivado import XilinxVivadoToolchain
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from liteeth.common import *
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from liteeth.phy import LiteEthPHY
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from liteeth.core import LiteEthUDPIPCore
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, platform, clk_freq=int(166e6),
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mac_address = 0x10e2d5000000,
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ip_address = "192.168.1.50"):
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sys_clk_freq = int((1/(platform.default_clk_period))*1e9)
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type = None,
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csr_data_width = 32,
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with_uart = False,
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ident = "LiteEth Base Design",
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with_timer = False
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)
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# Serial Wishbone Bridge
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serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
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self.submodules += serial_bridge
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self.add_wb_master(serial_bridge.wishbone)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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# Ethernet PHY and UDP/IP stack
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self.submodules.ethphy = ethphy = LiteEthPHY(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"),
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clk_freq = clk_freq)
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self.add_csr("ethphy")
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self.submodules.ethcore = ethcore = LiteEthUDPIPCore(
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phy = ethphy,
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mac_address = mac_address,
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ip_address = ip_address,
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clk_freq = clk_freq)
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self.add_csr("ethcore")
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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self.crg.cd_sys.clk.attr.add("keep")
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ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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ethphy.crg.cd_eth_rx.clk,
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ethphy.crg.cd_eth_tx.clk)
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# BaseSoCDevel -------------------------------------------------------------------------------------
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class BaseSoCDevel(BaseSoC):
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def __init__(self, platform):
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from litescope import LiteScopeAnalyzer
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BaseSoC.__init__(self, platform)
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analyzer_signals = [
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# MAC interface
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self.ethcore.mac.core.sink.valid,
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self.ethcore.mac.core.sink.last,
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self.ethcore.mac.core.sink.ready,
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self.ethcore.mac.core.sink.data,
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self.ethcore.mac.core.source.valid,
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self.ethcore.mac.core.source.last,
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self.ethcore.mac.core.source.ready,
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self.ethcore.mac.core.source.data,
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# ICMP interface
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self.ethcore.icmp.echo.sink.valid,
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self.ethcore.icmp.echo.sink.last,
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self.ethcore.icmp.echo.sink.ready,
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self.ethcore.icmp.echo.sink.data,
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self.ethcore.icmp.echo.source.valid,
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self.ethcore.icmp.echo.source.last,
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self.ethcore.icmp.echo.source.ready,
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self.ethcore.icmp.echo.source.data,
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# IP interface
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self.ethcore.ip.crossbar.master.sink.valid,
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self.ethcore.ip.crossbar.master.sink.last,
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self.ethcore.ip.crossbar.master.sink.ready,
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self.ethcore.ip.crossbar.master.sink.data,
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self.ethcore.ip.crossbar.master.sink.ip_address,
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self.ethcore.ip.crossbar.master.sink.protocol,
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# State machines
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self.ethcore.icmp.rx.fsm,
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self.ethcore.icmp.tx.fsm,
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self.ethcore.arp.rx.fsm,
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self.ethcore.arp.tx.fsm,
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self.ethcore.arp.table.fsm,
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self.ethcore.ip.rx.fsm,
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self.ethcore.ip.tx.fsm,
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self.ethcore.udp.rx.fsm,
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self.ethcore.udp.tx.fsm
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]
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="test/analyzer.csv")
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self.add_csr("analyzer")
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default_subtarget = BaseSoC
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