liteeth/liteeth
Florent Kermarrec 7a988bee22 core: Add initial/minimal DHCP support to hardware stack.
Ex of use in a  SoC that issues a DHCP request per second:

from liteeth.core.dhcp import LiteEthDHCP

from migen.genlib.misc import WaitTimer

# Signals.
ip_address  = Signal(32)
mac_address = Signal(48, reset=0x10e2d5000001)

# Request Timer.
self.dhcp_timer = dhcp_timer = WaitTimer(int(sys_clk_freq/2))
self.comb += self.dhcp_timer.wait.eq(~self.dhcp_timer.done)

# DHCP.
dhcp_port = self.ethcore_etherbone.udp.crossbar.get_port(68, dw=32, cd="sys")
self.dhcp = dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=sys_clk_freq)
self.comb += [
    dhcp.start.eq(self.dhcp_timer.done),
    dhcp.mac_address.eq(mac_address),
]

self.sync += [
    If(dhcp.done,
        ip_address.eq(dhcp.offered_ip_address)
    )
]
2023-07-03 17:44:48 +02:00
..
core core: Add initial/minimal DHCP support to hardware stack. 2023-07-03 17:44:48 +02:00
frontend frontend/stream: Add 16-bit data-width support. 2023-06-28 11:02:37 +02:00
mac liteeth/mac: Review/Minor changes to TXSlots write-only mode. 2023-07-03 10:50:07 +02:00
phy phy/usp_gtX_1000basex: Add 156.25MHz refclk_freq support in addition of 200MHz. 2023-06-23 12:43:35 +02:00
software software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default). 2020-11-24 19:40:18 +01:00
__init__.py init repo 2015-09-07 13:29:34 +02:00
common.py frontend/stream: Add packet support and remove send_level. 2022-07-29 14:58:25 +02:00
crossbar.py crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design. 2022-01-26 10:51:07 +01:00
gen.py liteeth_gen/sgmii: Expose link_up status. 2023-06-28 11:09:19 +02:00
packet.py packet.py: fix typo in Packetizer 2022-04-19 01:15:10 +02:00