liteeth/bench
Florent Kermarrec e0f053e7a2 bench: Set margin to 0 on 1000/2500BaseX reference clock generation. 2024-07-10 15:39:04 +02:00
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arty.py global: Use new WaitTimer integrated cast to int. 2023-08-01 14:42:16 +02:00
butterstick.py bench: Update. 2023-06-13 14:13:03 +02:00
colorlight_5a_75b.py bench: Update. 2023-06-13 14:13:03 +02:00
genesys2.py bench: Update. 2023-06-13 14:13:03 +02:00
kc705.py bench: Set margin to 0 on 1000/2500BaseX reference clock generation. 2024-07-10 15:39:04 +02:00
kcu105.py bench: Set margin to 0 on 1000/2500BaseX reference clock generation. 2024-07-10 15:39:04 +02:00
sim.py bench: Update. 2023-06-13 14:13:03 +02:00
test_etherbone.py bench: Update. 2023-06-13 14:13:03 +02:00
test_udp_streamer.py bench: Update. 2023-06-13 14:13:03 +02:00
xcu1525.py bench: Set margin to 0 on 1000/2500BaseX reference clock generation. 2024-07-10 15:39:04 +02:00
xu8_st1.py bench: Set margin to 0 on 1000/2500BaseX reference clock generation. 2024-07-10 15:39:04 +02:00