Florent Kermarrec aad9de7e53 frontend/stream/LiteEthStream2UDPTX: Add optional CSR to allow dynamic configuration (Enable, IP Address and UDP Port).		2024-12-13 21:27:47 +01:00
..
core	liteeth/core/__init__.py: Switch to LiteXModule.	2024-09-20 16:19:03 +02:00
frontend	frontend/stream/LiteEthStream2UDPTX: Add optional CSR to allow dynamic configuration (Enable, IP Address and UDP Port).	2024-12-13 21:27:47 +01:00
mac	mac/sram: Minor cosmetic cleanup.	2024-10-15 09:17:42 +02:00
phy	phy: Add initial Ultrascale+ GTYE4 10GBASE-R PHY.	2024-12-12 14:41:21 +01:00
software	software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).	2020-11-24 19:40:18 +01:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth.	2023-07-10 11:13:52 +02:00
crossbar.py	crossbar: Switch to LiteXModule.	2023-07-10 09:53:45 +02:00
gen.py	phy/usp_gth/gty_1000basex: Add refclk_from_fabric parameter to allow selecting GTGREFCLK or GTREFCLK0.	2024-11-25 09:21:17 +01:00
packet.py	packet: Switch to LiteX/Module.	2023-07-10 10:24:37 +02:00