liteeth/liteeth
Florent Kermarrec b7443f5fd3 gen/mac: Allow 16-bit data_width. 2024-04-04 13:36:16 +02:00
..
core core/arp/LiteEthARPTX: Simplify last_be generation. 2024-04-04 13:35:57 +02:00
frontend frontend/etherbone: Enable TX/RX buffer on UDP Port when requesting it (and others cosmetic cleanups). 2024-04-04 13:09:17 +02:00
mac gen/mac: Allow 16-bit data_width. 2024-04-04 13:36:16 +02:00
phy phy/a7_gtp: Allow using GTGREFCLK0/1 input as reference clocks. 2024-04-04 10:50:47 +02:00
software
__init__.py
common.py core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth. 2023-07-10 11:13:52 +02:00
crossbar.py
gen.py gen/mac: Allow 16-bit data_width. 2024-04-04 13:36:16 +02:00
packet.py packet: Switch to LiteX/Module. 2023-07-10 10:24:37 +02:00