Florent Kermarrec c250bb1485 mac/crc/LiteEthMACCRC32Inserter: Simplify crc.ce logic.		2024-04-04 13:06:59 +02:00
..
core	core/__init__: LiteEthUDPIPCore, LiteEthIPCore: expose interface & endianness at LiteEthUDPIPCore constructor. LiteEthIPCore: don't hardcode interface, pass macaddr and endianness to LiteEthMAC	2023-10-23 16:18:28 +02:00
frontend	frontend/stream/LiteEthStream2UDPTX: Latch ip_address/udp_port in Idle state.	2023-07-18 16:38:13 +02:00
mac	mac/crc/LiteEthMACCRC32Inserter: Simplify crc.ce logic.	2024-04-04 13:06:59 +02:00
phy	phy/a7_gtp: Allow using GTGREFCLK0/1 input as reference clocks.	2024-04-04 10:50:47 +02:00
software	software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default).	2020-11-24 19:40:18 +01:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth.	2023-07-10 11:13:52 +02:00
crossbar.py	crossbar: Switch to LiteXModule.	2023-07-10 09:53:45 +02:00
gen.py	phy/a7_1000basex: Add parameters to allow selecting TX/RX Clock Managment Modules (PLL or MMCM) and buffer types.	2024-03-22 12:28:24 +01:00
packet.py	packet: Switch to LiteX/Module.	2023-07-10 10:24:37 +02:00