119 lines
3.9 KiB
Python
Executable File
119 lines
3.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Yehowshua Immanuel <yimmanuel3@gatech.edu>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.boards.platforms import versa_ecp5
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.common import *
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.core import LiteEthUDPIPCore
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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# clk / rst
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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# pll
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# UDPLoopback ------------------------------------------------------------------------------------------
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class UDPLoopback(SoCMini):
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def __init__(self, platform):
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sys_clk_freq = int(150e6)
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SoCMini.__init__(self, platform, sys_clk_freq, ident="UDPLoopback", ident_version=True)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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self.submodules.eth_phy = LiteEthPHYRGMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"))
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self.add_csr("eth_phy")
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# core
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self.submodules.eth_core = LiteEthUDPIPCore(
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phy = self.eth_phy,
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mac_address = 0x10e2d5000000,
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ip_address = "192.168.1.50",
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clk_freq = sys_clk_freq)
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# add udp loopback on port 6000 with dw=8
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self.add_udp_loopback(6000, 8, 128, "loopback_8")
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# add udp loopback on port 8000 with dw=32
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self.add_udp_loopback(8000, 32, 128, "loopback_32")
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# timing constraints
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self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep")
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self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9/125e6)
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def add_udp_loopback(self, port, dw, depth, name=None):
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port = self.eth_core.udp.crossbar.get_port(port, dw)
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buf = stream.SyncFIFO(eth_udp_user_description(dw), depth//(dw//8))
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if name is None:
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self.submodules += buf
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else:
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setattr(self.submodules, name, buf)
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self.comb += Port.connect(port, buf)
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# Load ---------------------------------------------------------------------------------------------
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def load():
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import os
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f = open("ecp5-versa5g.cfg", "w")
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f.write(
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"""
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
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""")
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f.close()
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os.system("openocd -f ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/gateware/top.svf; exit\"")
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# Build --------------------------------------------------------------------------------------------
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def main():
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if "load" in sys.argv[1:]:
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load()
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exit()
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else:
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platform = versa_ecp5.Platform(toolchain="trellis")
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soc = UDPLoopback(platform)
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builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
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vns = builder.build()
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if __name__ == "__main__":
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main()
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