72 lines
2.7 KiB
Python
72 lines
2.7 KiB
Python
from litex.gen import *
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from litex.gen.sim.generic import run_simulation
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from litex.soc.interconnect import wishbone
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from liteeth.common import *
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from liteeth.core import LiteEthUDPIPCore
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from test.common import *
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from test.model import phy, mac, arp, ip, udp
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self, dw=8):
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self.dw = dw
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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udp_port = self.core.udp.crossbar.get_port(0x5678, dw)
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self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw))
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self.submodules.logger = PacketLogger(eth_udp_user_description(dw))
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self.comb += [
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Record.connect(self.streamer.source, udp_port.sink),
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udp_port.sink.ip_address.eq(0x12345678),
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udp_port.sink.src_port.eq(0x1234),
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udp_port.sink.dst_port.eq(0x5678),
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udp_port.sink.length.eq(64//(dw//8)),
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Record.connect(udp_port.source, self.logger.sink)
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]
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# use sys_clk for each clock_domain
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal()),
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self.cd_eth_rx.rst.eq(ResetSignal()),
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self.cd_eth_tx.clk.eq(ClockSignal()),
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self.cd_eth_tx.rst.eq(ResetSignal()),
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]
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def gen_simulation(self, selfp):
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selfp.cd_eth_rx.rst = 1
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selfp.cd_eth_tx.rst = 1
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yield
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selfp.cd_eth_rx.rst = 0
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selfp.cd_eth_tx.rst = 0
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for i in range(100):
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yield
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while True:
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packet = Packet([i for i in range(64//(self.dw//8))])
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yield from self.streamer.send(packet)
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yield from self.logger.receive()
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# check results
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s, l, e = check(packet, self.logger.packet)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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run_simulation(TB(8), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(16), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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run_simulation(TB(32), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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