Victor Suarez Rovere 5f14bd4a7f add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)		2022-10-31 20:43:53 -03:00
..
__init__.py	README: update and rename example_designs to examples	2018-08-31 08:26:37 +02:00
axi-lite-mii.yml	add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)	2022-10-31 20:43:53 -03:00
udp_s7phyrgmii.yml	liteeth_gen: Add data_width support (For 32/8-bit datapath).	2022-05-16 13:38:05 +02:00
wishbone_mii.yml	liteeth_gen: Add toolchain support/parameter.	2022-01-26 09:57:43 +01:00