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liteeth/test
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Florent Kermarrec f55ce1aac6 core/mac: simplify/improve performance of LiteEthMACSRAMReader 
now read data from sram on every clock cycle, allow lower system clock frequency (tested with 50MHz system clock / 125MHz ethernet clock)
2016-04-03 22:53:02 +02:00
..
model test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00
arp_tb.py test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00
etherbone_tb.py test: finish etherbone_tb (simulator limitation removed) 2016-03-23 09:48:02 +01:00
icmp_tb.py test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00
ip_tb.py test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00
mac_core_tb.py test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00
mac_wishbone_tb.py core/mac: simplify/improve performance of LiteEthMACSRAMReader 2016-04-03 22:53:02 +02:00
Makefile test: fix model_tb 2016-03-31 00:25:50 +02:00
udp_tb.py test: use passive generators and some cleanup 2016-03-23 01:42:35 +01:00