litescope/example_designs/targets/simple.py

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from migen import *
from migen.genlib.io import CRG
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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class LiteScopeSoC(SoCCore):
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csr_map = {
"io": 16,
"analyzer": 17
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
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SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
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with_uart=False,
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ident="Litescope example design",
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with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8)
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for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.io.output[i])
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except:
pass
# use name override to keep naming in capture
counter = Signal(4, name_override="counter")
counter0 = Signal(name_override="counter0")
counter1 = Signal(name_override="counter1")
counter2 = Signal(name_override="counter2")
counter3 = Signal(name_override="counter3")
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self.sync += counter.eq(counter + 1)
self.comb += [
counter0.eq(counter[0]),
counter1.eq(counter[1]),
counter2.eq(counter[2]),
counter3.eq(counter[3]),
]
# group for vcd capture
vcd_group = [
counter
]
# group for sigrok capture (no bus support)
sigrok_group = [
counter0,
counter1,
counter2,
counter3
]
analyzer_signals = {
0 : vcd_group,
1 : sigrok_group
}
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
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def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
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default_subtarget = LiteScopeSoC