for now use our fork of migen

example_designs/make.py

@@ -7,8 +7,8 @@ import subprocess
 import struct
 import importlib
 
-from migen.fhdl import verilog
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl import verilog
+from litex.gen.fhdl.structure import _Fragment
 
 from litex.build.tools import write_to_file
 from litex.build.xilinx.common import *

example_designs/targets/core.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.io import CRG
+from litex.gen import *
+from litex.gen.genlib.io import CRG
 
 from targets import *
 

example_designs/targets/simple.py

@@ -1,4 +1,4 @@
-from migen.genlib.io import CRG
+from litex.gen.genlib.io import CRG
 
 from litescope.common import *
 from litescope.core.port import LiteScopeTerm

litescope/common.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.fsm import FSM, NextState
-from migen.fhdl.specials import Memory
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
+from litex.gen.fhdl.specials import Memory
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.stream import *

litescope/software/driver/logic_analyzer.py

@@ -1,5 +1,5 @@
 from struct import *
-from migen.fhdl.structure import *
+from litex.gen.fhdl.structure import *
 from litescope.software.dump import *
 from litescope.software.driver.truthtable import *