test/analyzer_tb: retrieve and print data
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@ -14,7 +14,7 @@ example_designs:
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cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream
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cd ../example_designs && $(PYTHON) make.py -t core build-core
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all: dump_tb example_designs
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all: dump_tb analyzer_tb example_designs
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clean:
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rm -f dump.*
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@ -13,18 +13,27 @@ class TB(Module):
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def main_generator(dut):
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yield dut.analyzer.frontend.trigger.value.storage.eq(0x0080)
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yield dut.analyzer.frontend.trigger.mask.storage.eq(0xfff0)
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yield dut.analyzer.frontend.subsampler.value.storage.eq(1)
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yield dut.analyzer.frontend.subsampler.value.storage.eq(0)
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yield
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yield dut.analyzer.storage.length.storage.eq(32)
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yield dut.analyzer.storage.offset.storage.eq(16)
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yield dut.analyzer.storage.length.storage.eq(64)
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yield dut.analyzer.storage.offset.storage.eq(32)
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for i in range(16):
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yield
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yield dut.analyzer.storage.start.re.eq(1)
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yield
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yield dut.analyzer.storage.start.re.eq(0)
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yield
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for i in range(1024):
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while not (yield dut.analyzer.storage.idle.status):
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yield
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data = []
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while (yield dut.analyzer.storage.mem_valid.status):
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data.append((yield dut.analyzer.storage.mem_data.status))
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yield dut.analyzer.storage.mem_ready.re.eq(1)
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yield dut.analyzer.storage.mem_ready.r.eq(1)
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yield
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print(data)
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print(len(data))
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print(data[32])
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if __name__ == "__main__":
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tb = TB()
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