Hardware
/
litescope
mirror of https://github.com/enjoy-digital/litescope.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test/test_analzer: Update.

This commit is contained in:
Florent Kermarrec 2022-03-14 10:21:57 +01:00
parent 13813457d7
commit 3fb1018737
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
test/test_analyzer.py
View File

@ -33,19 +33,19 @@ class TestAnalyzer(unittest.TestCase):
# Wait capture
while not (yield from dut.analyzer.storage.done.read()):
yield
# Reade captured datas
while (yield from dut.analyzer.storage.mem_valid.read()):
# Read captured datas
while (yield from dut.analyzer.storage.mem_level.read()) > 0:
dut.data.append((yield from dut.analyzer.storage.mem_data.read()))
yield
class DUT(Module):
def __init__(self):
counter = Signal(16)
counter = Signal(32)
self.sync += counter.eq(counter + 1)
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
dut = DUT()
generators = {"sys" : [generator(dut)]}
clocks = {"sys": 10, "scope": 10}
run_simulation(dut, generators, clocks)
self.assertEqual(dut.data, [524 + 3*i for i in range(256)])
run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
self.assertEqual(dut.data, [524 + 3*i for i in range(len(dut.data))])