test/test_analzer: Update.
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@ -33,19 +33,19 @@ class TestAnalyzer(unittest.TestCase):
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# Wait capture
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# Wait capture
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while not (yield from dut.analyzer.storage.done.read()):
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while not (yield from dut.analyzer.storage.done.read()):
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yield
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yield
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# Reade captured datas
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# Read captured datas
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while (yield from dut.analyzer.storage.mem_valid.read()):
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while (yield from dut.analyzer.storage.mem_level.read()) > 0:
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dut.data.append((yield from dut.analyzer.storage.mem_data.read()))
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dut.data.append((yield from dut.analyzer.storage.mem_data.read()))
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yield
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yield
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class DUT(Module):
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class DUT(Module):
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def __init__(self):
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def __init__(self):
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counter = Signal(16)
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counter = Signal(32)
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self.sync += counter.eq(counter + 1)
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self.sync += counter.eq(counter + 1)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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dut = DUT()
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dut = DUT()
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generators = {"sys" : [generator(dut)]}
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generators = {"sys" : [generator(dut)]}
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clocks = {"sys": 10, "scope": 10}
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clocks = {"sys": 10, "scope": 10}
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run_simulation(dut, generators, clocks)
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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self.assertEqual(dut.data, [524 + 3*i for i in range(256)])
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self.assertEqual(dut.data, [524 + 3*i for i in range(len(dut.data))])
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