frontend/logic_analyzer: add Converter for the cases where clk_domain frequency > system frequency
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@ -6,10 +6,11 @@ from litex.build.tools import write_to_file
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class LiteScopeLogicAnalyzer(Module, AutoCSR):
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def __init__(self, layout, depth, clk_domain="sys",
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def __init__(self, layout, depth,
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with_input_buffer=False,
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with_rle=False, rle_length=256,
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with_subsampler=False):
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with_subsampler=False,
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clk_domain="sys", clk_ratio=1):
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self.layout = layout
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self.data = Cat(*layout)
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self.dw = len(self.data)
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@ -17,11 +18,12 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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self.dw = max(self.dw, log2_int(rle_length))
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self.dw += 1
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self.depth = depth
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self.clk_domain = clk_domain
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self.with_rle = with_rle
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self.rle_length = rle_length
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self.with_input_buffer = with_input_buffer
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self.with_subsampler = with_subsampler
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self.clk_domain = clk_domain
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self.clk_ratio = clk_ratio
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self.sink = stream.Endpoint(data_layout(self.dw))
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self.comb += [
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@ -29,8 +31,8 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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self.sink.data.eq(self.data)
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]
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self.submodules.trigger = trigger = LiteScopeTrigger(self.dw)
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self.submodules.recorder = recorder = LiteScopeRecorder(self.dw, self.depth)
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self.submodules.trigger = trigger = LiteScopeTrigger(self.dw*self.clk_ratio)
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self.submodules.recorder = recorder = LiteScopeRecorder(self.dw*self.clk_ratio, self.depth)
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def do_finalize(self):
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sink = self.sink
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@ -38,20 +40,24 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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if self.with_input_buffer:
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input_buffer = Buffer(self.sink.description)
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if self.clk_domain is not "sys":
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self.submodules += RenameClockDomains(input_buffer, clk_domain)
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self.submodules += ClockDomainsRenamer(self.clk_domain)(input_buffer)
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else:
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self.submodules += input_buffer
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self.comb += sink.connect(intput_buffer.sink)
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sink = intput_buffer.source
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sink = input_buffer.source
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# clock domain crossing (optional, required when capture_clk is not sys_clk)
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# XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
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if self.clk_domain is not "sys":
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self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
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self.submodules += RenameClockDomains(self.fifo,
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{"write": self.clk_domain, "read": "sys"})
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self.comb += sink.connect(self.fifo.sink)
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sink = self.fifo.source
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converter = StrideConverter(data_layout(self.dw),
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data_layout(self.dw*self.clk_ratio))
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self.submodules += ClockDomainsRenamer(self.clk_domain)(converter)
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fifo = AsyncFIFO(converter.source.description, 32)
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self.submodules += ClockDomainsRenamer({"write": self.clk_domain, "read": "sys"})(fifo)
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self.comb += [
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sink.connect(converter.sink),
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converter.source.connect(fifo.sink)
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]
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sink = fifo.source
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# connect trigger
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self.comb += [
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@ -75,7 +81,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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self.rle.external_enable.eq(self.recorder.post_hit)
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]
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else:
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self.submodules.delay_buffer = Buffer(self.sink.description)
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self.submodules.delay_buffer = Buffer(sink.description)
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self.comb += [
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sink.connect(self.delay_buffer.sink),
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self.delay_buffer.source.connect(self.recorder.data_sink)
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@ -88,6 +94,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
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r += format_line("config", "dw", str(self.dw))
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r += format_line("config", "depth", str(self.depth))
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r += format_line("config", "with_rle", str(int(self.with_rle)))
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r += format_line("config", "clk_ratio", str(int(self.clk_ratio)))
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if not isinstance(self.layout, tuple):
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self.layout = [self.layout]
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for e in self.layout:
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@ -1,5 +1,6 @@
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from struct import *
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from litex.gen.fhdl.structure import *
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from litescope.software.dump.common import *
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from litescope.software.dump import *
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from litescope.software.driver.truthtable import *
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@ -116,6 +117,12 @@ class LiteScopeLogicAnalyzerDriver():
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while self.recorder_source_valid.read():
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self.data.append(self.recorder_source_data.read())
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self.recorder_source_ready.write(1)
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if self.clk_ratio > 1:
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new_data = DumpData(self.dw)
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for data in self.data:
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for i in range(self.clk_ratio):
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new_data.append(*get_bits([data], i*self.dw, (i+1)*self.dw))
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self.data = new_data
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if self.with_rle:
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if self.rle_enable.read():
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self.data = self.data.decode_rle()
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