uniformize litex cores
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Florent Kermarrec
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LICENSE
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LICENSE
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Unless otherwise noted, LiteScope is copyright (C) 2015 Florent Kermarrec.
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Unless otherwise noted, LiteScope is Copyright 2012-2018 / EnjoyDigital
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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48
README
48
README
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/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
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/____/_/\__/\__/___/\__/\___/ .__/\__/
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/_/
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Copyright 2012-2017 / EnjoyDigital
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Copyright 2015-2018 / EnjoyDigital
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A small footprint and configurable embedded FPGA
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logic analyzer core powered by LiteX
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A small footprint and configurable Logic Analyzer
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core powered by LiteX
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[> Intro
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--------
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LiteScope is a small footprint and configurable embedded logic analyzer that you
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LiteScope provides a small footprint and configurable embedded logic analyzer that you
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can use in your FPGA and aims to provide a free, portable and flexible
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alternative to vendor's solutions!
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@ -18,9 +18,6 @@ LiteScope is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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@ -40,13 +37,14 @@ design flow by generating the verilog rtl that you will use as a standard core.
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- Data storage in block rams
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- Bridges:
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- UART2Wishbone (provided by LiteX)
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- Ethernet2Wishbone ("Etherbone") (when used with LiteEth)
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- PCIe2Wishbone (when used with LitePCIe)
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- Ethernet2Wishbone ("Etherbone") (provided by LiteEth)
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- PCIe2Wishbone (provided by LitePCIe)
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- Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...
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[> Proven
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---------
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LiteScope has already been used to investigate issues on commercial and open-source designs.
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LiteScope has already been used to investigate issues on several commercial or
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open-source designs.
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[> Possible improvements
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------------------------
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@ -58,9 +56,7 @@ LiteScope has already been used to investigate issues on commercial and open-sou
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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enjoy-digital.fr.
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[> Getting started
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------------------
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@ -69,20 +65,18 @@ devel [AT] lists.m-labs.hk.
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2. Obtain LiteX and install it:
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git clone https://github.com/enjoy-digital/litex --recursive
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cd litex
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python3 setup.py install
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python3 setup.py develop
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cd ..
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3. Build and load test design:
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go to example_designs/
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./make.py -p [your_platform] all load-bitstream
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Supported platforms are the ones already supported by Mibuild:
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de0nano, m1, mixxeo, kc705, zedboard...
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3. TODO: add/describe example design(s)
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4. Test design:
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go to test and run:
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litex_server --port your_serial_port
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python3 test_io.py (led blinker)
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python3 test_analyzer.py (capture counter with analyzer)
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[> Tests
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--------
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Unit tests are available in ./test/.
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To run all the unit tests:
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./setup.py test
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Tests can also be run individually:
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python3 -m unittest test.test_name
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[> License
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----------
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@ -101,10 +95,10 @@ do them if possible:
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteScope is mainly developed and maintained by EnjoyDigital.
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LiteScope is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteScope or if you are already a happy user
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and would like to extend it for your needs, EnjoyDigital can provide standard
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If you would like to know more about LiteScope or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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