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uniformize litex cores

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Florent Kermarrec 2018-02-22 10:18:17 +01:00
parent 985585f0b9
commit 62c4bdd102
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LICENSE
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@ -1,4 +1,4 @@
Unless otherwise noted, LiteScope is copyright (C) 2015 Florent Kermarrec. Unless otherwise noted, LiteScope is Copyright 2012-2018 / EnjoyDigital
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:

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README
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@ -3,14 +3,14 @@
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_) / /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
/____/_/\__/\__/___/\__/\___/ .__/\__/ /____/_/\__/\__/___/\__/\___/ .__/\__/
/_/ /_/
Copyright 2012-2017 / EnjoyDigital Copyright 2015-2018 / EnjoyDigital
A small footprint and configurable embedded FPGA A small footprint and configurable Logic Analyzer
logic analyzer core powered by LiteX core powered by LiteX
[> Intro [> Intro
-------- --------
LiteScope is a small footprint and configurable embedded logic analyzer that you LiteScope provides a small footprint and configurable embedded logic analyzer that you
can use in your FPGA and aims to provide a free, portable and flexible can use in your FPGA and aims to provide a free, portable and flexible
alternative to vendor's solutions! alternative to vendor's solutions!
@ -18,9 +18,6 @@ LiteScope is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.
Since Python is used to describe the HDL, the core is highly and easily Since Python is used to describe the HDL, the core is highly and easily
configurable. configurable.
@ -40,13 +37,14 @@ design flow by generating the verilog rtl that you will use as a standard core.
- Data storage in block rams - Data storage in block rams
- Bridges: - Bridges:
- UART2Wishbone (provided by LiteX) - UART2Wishbone (provided by LiteX)
- Ethernet2Wishbone ("Etherbone") (when used with LiteEth) - Ethernet2Wishbone ("Etherbone") (provided by LiteEth)
- PCIe2Wishbone (when used with LitePCIe) - PCIe2Wishbone (provided by LitePCIe)
- Exports formats: .vcd, .sr(sigrok), .csv, .py, etc... - Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...
[> Proven [> Proven
--------- ---------
LiteScope has already been used to investigate issues on commercial and open-source designs. LiteScope has already been used to investigate issues on several commercial or
open-source designs.
[> Possible improvements [> Possible improvements
------------------------ ------------------------
@ -58,9 +56,7 @@ LiteScope has already been used to investigate issues on commercial and open-sou
- ... See below Support and consulting :) - ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT] If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list enjoy-digital.fr.
devel [AT] lists.m-labs.hk.
[> Getting started [> Getting started
------------------ ------------------
@ -69,20 +65,18 @@ devel [AT] lists.m-labs.hk.
2. Obtain LiteX and install it: 2. Obtain LiteX and install it:
git clone https://github.com/enjoy-digital/litex --recursive git clone https://github.com/enjoy-digital/litex --recursive
cd litex cd litex
python3 setup.py install python3 setup.py develop
cd .. cd ..
3. Build and load test design: 3. TODO: add/describe example design(s)
go to example_designs/
./make.py -p [your_platform] all load-bitstream
Supported platforms are the ones already supported by Mibuild:
de0nano, m1, mixxeo, kc705, zedboard...
4. Test design: [> Tests
go to test and run: --------
litex_server --port your_serial_port Unit tests are available in ./test/.
python3 test_io.py (led blinker) To run all the unit tests:
python3 test_analyzer.py (capture counter with analyzer) ./setup.py test
Tests can also be run individually:
python3 -m unittest test.test_name
[> License [> License
---------- ----------
@ -101,10 +95,10 @@ do them if possible:
------------------------- -------------------------
We love open-source hardware and like sharing our designs with others. We love open-source hardware and like sharing our designs with others.
LiteScope is mainly developed and maintained by EnjoyDigital. LiteScope is developed and maintained by EnjoyDigital.
If you would like to know more about LiteScope or if you are already a happy user If you would like to know more about LiteScope or if you are already a happy
and would like to extend it for your needs, EnjoyDigital can provide standard user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services. commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten So feel free to contact us, we'd love to work with you! (and eventually shorten