enjoy-digital
GitHub
commit
66956cb88f
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#!/usr/bin/env python3
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from migen import *
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from litex.boards.platforms import arty
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from migen.genlib.io import CRG,DifferentialInput
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from litex.build.generic_platform import Subsignal
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from litex.build.generic_platform import Pins
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from litex.build.generic_platform import IOStandard
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from litex.soc.cores.clock import *
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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#
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# Use the 8 input on the dual PMOD connector B as input
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# Those are the fast and not so well protected pins.
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_serdes_io = [
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("serdes_io", 0,
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Subsignal("d0", Pins("E15"),IOStandard("LVCMOS33")),
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Subsignal("d1", Pins("E16"),IOStandard("LVCMOS33")),
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Subsignal("d2", Pins("D15"),IOStandard("LVCMOS33")),
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Subsignal("d3", Pins("C15"),IOStandard("LVCMOS33")),
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Subsignal("d4", Pins("J17"),IOStandard("LVCMOS33")),
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Subsignal("d5", Pins("J18"),IOStandard("LVCMOS33")),
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Subsignal("d6", Pins("K15"),IOStandard("LVCMOS33")),
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Subsignal("d7", Pins("J15"),IOStandard("LVCMOS33")),
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)
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]
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class SerdesInputSignal(Module):
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def __init__(self, pad):
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self.signals = Signal(8)
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#
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# Based on a 100MHz input clock and a 400MHz sample clock and
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# Measuring at ddr speed we are sampling at 800Mhz
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#
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self.specials += Instance("ISERDESE2",
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p_DATA_WIDTH=8, p_DATA_RATE="DDR",
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p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1, p_IOBDELAY="NONE",
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i_D=pad,
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i_CE1=1,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"),
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i_CLKDIV=ClockSignal("sys"),
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i_BITSLIP=0,
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o_Q8=self.signals[0], o_Q7=self.signals[1],
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o_Q6=self.signals[2], o_Q5=self.signals[3],
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o_Q4=self.signals[4], o_Q3=self.signals[5],
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o_Q2=self.signals[6], o_Q1=self.signals[7]
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)
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class SerdesIO(Module):
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def __init__(self,platform):
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platform.add_extension(_serdes_io)
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pads = platform.request("serdes_io")
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self.submodules.d0 = SerdesInputSignal(pads.d0)
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self.submodules.d1 = SerdesInputSignal(pads.d1)
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self.submodules.d2 = SerdesInputSignal(pads.d2)
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self.submodules.d3 = SerdesInputSignal(pads.d3)
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self.submodules.d4 = SerdesInputSignal(pads.d4)
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self.submodules.d5 = SerdesInputSignal(pads.d5)
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self.submodules.d6 = SerdesInputSignal(pads.d6)
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self.submodules.d7 = SerdesInputSignal(pads.d7)
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platform.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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""")
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys4x.clk.attr.add("keep")
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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class LiteScopeSoC(SoCCore):
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csr_map = {
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"analyzer": 17
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform):
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sys_clk_freq = int(100e6)
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SoCCore.__init__(self, platform, sys_clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Fast scope", ident_version=True,
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with_timer=False
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)
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self.submodules.serdes = SerdesIO(platform)
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# crg
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self.submodules.crg = _CRG(platform,sys_clk_freq)
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# bridge
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self.add_cpu(UARTWishboneBridge(platform.request("serial"),
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sys_clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu.wishbone)
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# Litescope Analyzer
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analyzer_groups = {}
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# Analyzer group
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analyzer_groups[0] = [
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self.serdes.d0.signals,
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self.serdes.d1.signals,
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self.serdes.d2.signals,
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self.serdes.d3.signals,
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]
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# analyzer
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
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def do_exit(self, vns):
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self.analyzer.export_csv(vns, "test/analyzer.csv")
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platform = arty.Platform()
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soc = LiteScopeSoC(platform)
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vns = platform.build(soc)
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#
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# Create csr and analyzer files
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#
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soc.finalize()
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csr_regions = soc.get_csr_regions()
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csr_constants = soc.get_constants()
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from litex.build.tools import write_to_file
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from litex.soc.integration import cpu_interface
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csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
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write_to_file("test/csr.csv", csr_csv)
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soc.do_exit(vns)
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#
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# Program
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#
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platform.create_programmer().load_bitstream("build/top.bit")
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@ -0,0 +1,27 @@
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#!/usr/bin/env python3
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from litex import RemoteClient
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from litescope import LiteScopeAnalyzerDriver
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wb = RemoteClient()
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wb.open()
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# # #
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subsample = 1
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
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analyzer.configure_subsampler(subsample)
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analyzer.configure_group(0)
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analyzer.run(offset=32, length=512)
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analyzer.wait_done()
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analyzer.upload()
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#
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# Convert parallel input back to a flaten view (e.g. the 8 bits values are flattened)
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#
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analyzer.save("dump.vcd",flatten=True)
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# # #
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wb.close()
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@ -126,7 +126,7 @@ class LiteScopeAnalyzerDriver:
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print("")
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return self.data
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def save(self, filename, samplerate=None):
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def save(self, filename, samplerate=None, flatten=False):
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if self.debug:
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print("[writing to " + filename + "]...")
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name, ext = os.path.splitext(filename)
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@ -140,7 +140,10 @@ class LiteScopeAnalyzerDriver:
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dump = SigrokDump(samplerate=samplerate)
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else:
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raise NotImplementedError
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dump.add_from_layout(self.layouts[self.group], self.data)
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if not flatten:
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dump.add_from_layout(self.layouts[self.group], self.data)
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else:
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dump.add_from_layout_flatten(self.layouts[self.group], self.data)
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dump.write(filename)
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def get_instant_value(self, group, name):
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@ -48,8 +48,8 @@ class DumpData(list):
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class DumpVariable:
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def __init__(self, name, width, values=[]):
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self.width = width
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self.name = name
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self.width = width
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self.values = [int(v)%2**width for v in values]
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def __len__(self):
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@ -64,12 +64,26 @@ class Dump:
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self.variables.append(variable)
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def add_from_layout(self, layout, variable):
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i = 0
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for s, n in layout:
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values = variable[i:i+n]
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values2x = [values[j//2] for j in range(len(values)*2)]
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self.add(DumpVariable(s, n, values2x))
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i += n
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offset = 0
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for name, sample_width in layout:
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values = variable[offset:offset+sample_width]
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values2x = [values[i//2] for i in range(len(values)*2)]
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self.add(DumpVariable(name, sample_width, values2x))
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offset += sample_width
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self.add(DumpVariable("scope_clk", 1, [1, 0]*(len(self)//2)))
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def add_from_layout_flatten(self, layout, variable):
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offset = 0
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for name, sample_width in layout:
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# The samples from the logic analyzer end up in an array of size sample size
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# and have n (number of channel) bits. The following does a bit slice on the array
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# elements (implemented above)
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values = variable[offset:offset+sample_width]
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values_flatten = [values[i//sample_width] >> (i % sample_width ) & 1 for i in range(len(values)*sample_width)]
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self.add(DumpVariable(name, 1, values_flatten))
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offset += sample_width
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# the clock.. might need some more love here. the clock pattern probably should be sample_width wide
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# e.g. 11110000 and not 10101010
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self.add(DumpVariable("scope_clk", 1, [1, 0]*(len(self)//2)))
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def __len__(self):
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