start adapting to new migen/litex

example_designs/make.py

@@ -7,21 +7,31 @@ import subprocess
 import struct
 import importlib
 
-from mibuild.tools import write_to_file
+from migen.fhdl import verilog
-from migen.util.misc import autotype
-from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
-from migen.bank.description import CSRStatus
-from mibuild import tools
-from mibuild.xilinx.common import *
 
-from misoclib.soc import cpuif
+from litex.build.tools import write_to_file
+from litex.build.xilinx.common import *
+
+from litex.soc.integration import cpu_interface
 
 litescope_path = "../"
 sys.path.append(litescope_path) # XXX
 from litescope.common import *
 
 
+def autotype(s):
+    if s == "True":
+        return True
+    elif s == "False":
+        return False
+    try:
+        return int(s, 0)
+    except ValueError:
+        pass
+    return s
+
+
 def _import(default, name):
     return importlib.import_module(default + "." + name)
 
@@ -56,8 +66,6 @@ all             clean, build-csr-csv, build-bitstream, load-bitstream.
 
     return parser.parse_args()
 
-# Note: misoclib need to be installed as a python library
-
 if __name__ == "__main__":
     args = _get_args()
 
@@ -79,7 +87,7 @@ if __name__ == "__main__":
                 raise ValueError("Target has no default platform, specify a platform with -p your_platform")
         else:
             platform_name = args.platform
-        platform_module = _import("mibuild.platforms", platform_name)
+        platform_module = _import("litex.boards.platforms", platform_name)
         platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
         platform = platform_module.Platform(**platform_kwargs)
 
@@ -153,7 +161,7 @@ RLE: {}
         subprocess.call(["rm", "-rf", "build/*"])
 
     if actions["build-csr-csv"]:
-        csr_csv = cpuif.get_csr_csv(csr_regions)
+        csr_csv = cpu_interface.get_csr_csv(csr_regions)
         write_to_file(args.csr_csv, csr_csv)
 
     if actions["build-core"]:

example_designs/targets/core.py

@@ -1,13 +1,13 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.io import CRG
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from mibuild.generic_platform import *
-from mibuild.xilinx.platform import XilinxPlatform
 
 from targets import *
 
-from misoclib.soc import SoC
+from litex.build.generic_platform import *
+from litex.build.xilinx.platform import XilinxPlatform
+
+from litex.soc.integration.soc_core import SoCCore
+from litex.soc.cores.uart.bridge import UARTWishboneBridge
 
 from litescope.core.port import LiteScopeTerm
 from litescope.frontend.inout import LiteScopeInOut
@@ -24,8 +24,6 @@ _io = [
     ("bus", 0, Pins(" ".join(["X" for i in range(128)])))
 ]
 
-from misoclib.com.uart.bridge import UARTWishboneBridge
-
 class CorePlatform(XilinxPlatform):
     name = "core"
     default_clk_name = "sys_clk"
@@ -36,21 +34,21 @@ class CorePlatform(XilinxPlatform):
         pass
 
 
-class Core(SoC):
+class Core(SoCCore):
     platform = CorePlatform()
     csr_map = {
         "logic_analyzer":    16
     }
-    csr_map.update(SoC.csr_map)
+    csr_map.update(SoCCore.csr_map)
 
     def __init__(self, platform, clk_freq=100*1000000):
         self.clk_freq = clk_freq
         self.clock_domains.cd_sys = ClockDomain("sys")
-        SoC.__init__(self, platform, clk_freq,
+        SoCCore.__init__(self, platform, clk_freq,
-            cpu_type="none",
+            cpu_type=None,
-            with_csr=True, csr_data_width=32,
+            csr_data_width=32,
             with_uart=False,
-            with_identifier=True,
+            ident="Litescope example design",
             with_timer=False
         )
         self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))

example_designs/targets/simple.py

@@ -1,28 +1,27 @@
 from migen.genlib.io import CRG
 
-from misoclib.soc import SoC
-
 from litescope.common import *
 from litescope.core.port import LiteScopeTerm
 from litescope.frontend.inout import LiteScopeInOut
 from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
 
-from misoclib.com.uart.bridge import UARTWishboneBridge
+from litex.soc.integration.soc_core import SoCCore
+from litex.soc.cores.uart.bridge import UARTWishboneBridge
 
-class LiteScopeSoC(SoC):
+class LiteScopeSoC(SoCCore):
     csr_map = {
         "inout" :          16,
         "logic_analyzer" : 17
     }
-    csr_map.update(SoC.csr_map)
+    csr_map.update(SoCCore.csr_map)
 
     def __init__(self, platform):
         clk_freq = int((1/(platform.default_clk_period))*1000000000)
-        SoC.__init__(self, platform, clk_freq,
+        SoCCore.__init__(self, platform, clk_freq,
-            cpu_type="none",
+            cpu_type=None,
-            with_csr=True, csr_data_width=32,
+            csr_data_width=32,
             with_uart=False,
-            with_identifier=True,
+            ident="Litescope example design",
             with_timer=False
         )
         self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))

litescope/common.py

@@ -1,19 +1,17 @@
-from migen.fhdl.std import *
+from migen import *
-from migen.bank.description import *
 from migen.genlib.fsm import FSM, NextState
-from migen.flow.actor import *
-from migen.genlib.misc import Counter
-from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
-from migen.flow.plumbing import Buffer
 from migen.fhdl.specials import Memory
 
+from litex.soc.interconnect.csr import *
+from litex.soc.interconnect.stream import *
+
 
 @ResetInserter()
 @CEInserter()
 class Counter(Module):
     def __init__(self, *args, increment=1, **kwargs):
         self.value = Signal(*args, **kwargs)
-        self.width = flen(self.value)
+        self.width = len(self.value)
         self.sync += self.value.eq(self.value+increment)
 
 

litescope/core/storage.py

@@ -1,5 +1,4 @@
 from litescope.common import *
-from migen.flow.plumbing import Buffer
 
 
 class LiteScopeSubSamplerUnit(Module):
@@ -73,7 +72,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
                 NextState("BYPASS")
             ).Elif(change | counter_done,
                 source.stb.eq(1),
-                source.data[:flen(counter.value)].eq(counter.value),
+                source.data[:len(counter.value)].eq(counter.value),
                 source.data[-1].eq(1),  # Set RLE bit
                 buf.q.ack.eq(source.ack),
                 If(source.ack,
@@ -113,7 +112,7 @@ class LiteScopeRecorderUnit(Module):
 
         # # #
 
-        fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True))
+        fifo = ResetInserter()(SyncFIFO(data_layout(dw), depth, buffered=True))
         self.submodules += fifo
 
         fsm = FSM(reset_state="IDLE")

litescope/core/trigger.py

@@ -1,4 +1,6 @@
 from litescope.common import *
+from functools import reduce
+from operator import and_
 
 
 class LiteScopeSumUnit(Module, AutoCSR):
@@ -30,7 +32,7 @@ class LiteScopeSumUnit(Module, AutoCSR):
 
         # drive source
         self.comb += [
-            source.stb.eq(optree("&", [sink.stb for sink in sinks])),
+            source.stb.eq(reduce(and_, [sink.stb for sink in sinks])),
             source.hit.eq(lut.dat_r)
         ]
         for i, sink in enumerate(sinks):

litescope/frontend/logic_analyzer.py

@@ -2,7 +2,7 @@ from litescope.common import *
 from litescope.core.trigger import LiteScopeTrigger
 from litescope.core.storage import LiteScopeSubSampler, LiteScopeRecorder, LiteScopeRunLengthEncoder
 
-from mibuild.tools import write_to_file
+from litex.build.tools import write_to_file
 
 
 class LiteScopeLogicAnalyzer(Module, AutoCSR):
@@ -12,7 +12,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
             with_subsampler=False):
         self.layout = layout
         self.data = Cat(*layout)
-        self.dw = flen(self.data)
+        self.dw = len(self.data)
         if with_rle:
             self.dw = max(self.dw, log2_int(rle_length))
             self.dw += 1
@@ -91,5 +91,5 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
         if not isinstance(self.layout, tuple):
             self.layout = [self.layout]
         for e in self.layout:
-            r += format_line("layout", vns.get_name(e), str(flen(e)))
+            r += format_line("layout", vns.get_name(e), str(len(e)))
         write_to_file(filename, r)