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examples: simplify/update

This commit is contained in:
Florent Kermarrec 2020-02-26 22:02:14 +01:00
parent daf10e9473
commit 9dd2e968e9
3 changed files with 35 additions and 60 deletions
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32
examples/targets/core.py
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@ -2,15 +2,13 @@
# License: BSD
from migen import *
from migen.genlib.io import CRG
from targets import *
from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.integration.soc_core import SoCMini
from litescope import LiteScopeAnalyzer
@ -25,41 +23,27 @@ _io = [
("bus", 0, Pins(128))
]
class CorePlatform(XilinxPlatform):
name = "core"
default_clk_name = "sys_clk"
def __init__(self):
XilinxPlatform.__init__(self, "", _io)
def do_finalize(self, *args, **kwargs):
pass
class Core(SoCCore):
class Core(SoCMini):
platform = CorePlatform()
csr_map = {
"analyzer": 16
}
csr_map.update(SoCCore.csr_map)
def __init__(self, platform, clk_freq=100*1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
SoCMini.__init__(self, platform, clk_freq, csr_data_width=32,
with_uart=True, uart_name="bridge",
ident="Litescope example design", ident_version=True,
)
bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.submodules.bridge = bridge
self.add_wb_master(bridge.wishbone)
self.bus = platform.request("bus")
self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"), 512)
self.add_csr("analyzer")
default_subtarget = Core

61
examples/targets/simple.py
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@ -4,65 +4,58 @@
from migen import *
from migen.genlib.io import CRG
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.integration.soc_core import SoCMini
from litescope import LiteScopeIO, LiteScopeAnalyzer
# LiteScope SoC ------------------------------------------------------------------------------------
class LiteScopeSoC(SoCCore):
csr_map = {
"io": 16,
"analyzer": 17
}
csr_map.update(SoCCore.csr_map)
class LiteScopeSoC(SoCMini):
def __init__(self, platform):
sys_clk_freq = int((1e9/platform.default_clk_period))
SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design", ident_version=True,
with_timer=False
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, sys_clk_freq,
csr_data_width = 32,
with_uart = True,
uart_name = "bridge",
ident = "Litescope example design",
ident_version = True,
)
# crg
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# bridge
bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
self.submodules.bridge = bridge
self.add_wb_master(bridge.wishbone)
# Litescope IO
# Litescope IO -----------------------------------------------------------------------------
self.submodules.io = LiteScopeIO(8)
self.add_csr("io")
for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer
# Litescope Analyzer -----------------------------------------------------------------------
analyzer_groups = {}
# counter group
# Counter group
counter = Signal(16, name_override="counter")
zero = Signal(name_override="zero")
zero = Signal(name_override="zero")
self.sync += counter.eq(counter + 1)
self.comb += zero.eq(counter == 0)
analyzer_groups[0] = [
zero,
counter
counter,
]
# communication group
# Communication group
analyzer_groups[1] = [
platform.lookup_request("serial").tx,
platform.lookup_request("serial").rx,
bridge.wishbone
self.bus.masters["uart_bridge"],
]
# fsm group
# FSM group
fsm = FSM(reset_state="STATE1")
self.submodules += fsm
fsm.act("STATE1",
@ -72,13 +65,11 @@ class LiteScopeSoC(SoCCore):
NextState("STATE1")
)
analyzer_groups[2] = [
fsm
fsm,
]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
# Analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
default_subtarget = LiteScopeSoC

2
test/test_examples.py
View File

@ -16,7 +16,7 @@ class TestExamples(unittest.TestCase):
os.system("python3 {} -t simple -p de0nano -Ob run False build-bitstream".format(make_script))
self.assertEqual(os.path.isfile("{}/build/litescopesoc_de0nano.v".format(root_dir)), True)
def test_simple_705(self):
def test_simple_kc705(self):
os.system("rm -rf {}/build".format(root_dir))
os.system("python3 {} -t simple -p kc705 -Ob run False build-bitstream".format(make_script))
self.assertEqual(os.path.isfile("{}/build/litescopesoc_kc705.v".format(root_dir)), True)