use new Record.connect omit parameter (replace leave_out)
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f8e3e63ef3
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@ -65,7 +65,7 @@ class FrontendSubSampler(Module, AutoCSR):
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self.comb += [
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self.comb += [
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done.eq(counter == value),
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done.eq(counter == value),
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self.sink.connect(self.source, leave_out=set(["valid"])),
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self.sink.connect(self.source, omit=set(["valid"])),
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self.source.valid.eq(self.sink.valid & done)
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self.source.valid.eq(self.sink.valid & done)
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]
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]
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@ -130,7 +130,7 @@ class AnalyzerStorage(Module, AutoCSR):
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)
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)
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fsm.act("WAIT",
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fsm.act("WAIT",
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self.wait.status.eq(1),
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self.wait.status.eq(1),
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self.sink.connect(mem.sink, leave_out=set(["hit"])),
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self.sink.connect(mem.sink, omit=set(["hit"])),
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If(self.sink.valid & (self.sink.hit != 0),
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If(self.sink.valid & (self.sink.hit != 0),
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NextState("RUN")
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NextState("RUN")
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),
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),
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@ -138,7 +138,7 @@ class AnalyzerStorage(Module, AutoCSR):
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)
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)
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fsm.act("RUN",
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fsm.act("RUN",
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self.run.status.eq(1),
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self.run.status.eq(1),
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self.sink.connect(mem.sink, leave_out=set(["hit"])),
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self.sink.connect(mem.sink, omit=set(["hit"])),
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If(~mem.sink.ready | (mem.level >= self.length.storage),
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If(~mem.sink.ready | (mem.level >= self.length.storage),
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NextState("IDLE"),
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NextState("IDLE"),
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mem.source.ready.eq(1)
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mem.source.ready.eq(1)
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