core: remove reset on scope clk
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@ -246,10 +246,7 @@ class LiteScopeAnalyzer(Module, AutoCSR):
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# create scope clock domain
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self.clock_domains.cd_scope = ClockDomain()
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self.comb += [
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self.cd_scope.clk.eq(ClockSignal(clock_domain)),
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self.cd_scope.rst.eq(ResetSignal(clock_domain))
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]
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self.comb += self.cd_scope.clk.eq(ClockSignal(clock_domain))
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# mux
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self.submodules.mux = _Mux(data_width, len(groups))
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