README: update
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Florent Kermarrec
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README
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README
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@ -9,7 +9,7 @@
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logic analyzer core powered by Migen
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[> Doc
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---------
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-------
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HTML : www.enjoy-digital.fr/litescope/
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PDF : www.enjoy-digital.fr/litescope.pdf
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@ -19,9 +19,9 @@ LiteScope is a small footprint and configurable embedded logic analyzer that you
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can use in your FPGA and aims to provide a free, portable and flexible
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alternative to vendor's solutions!
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LiteScope is part of MiSoC libraries whose aims are to lower entry level of complex
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FPGA cores by providing simple, elegant and efficient implementations of
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components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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LiteScope is part of EnjoyDigital's libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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@ -32,20 +32,14 @@ configurable.
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LiteScope uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteScope can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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LiteScope handles various export formats: .vcd, .sr(sigrok), .csv, .py...
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Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
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external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
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LiteScope can be used as MiSoC library or can be integrated with your standard
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design flow by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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- IO peek and poke with LiteScopeIO
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- Logic analyser with LiteScopeLA:
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------------
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- IO peek and poke with LiteScopeInOut
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- Logic analyser with LiteScopeLogicAnalyzer:
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- Various triggering modules: Term, Range, Edge (add yours! :)
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- Run Length Encoder to "compress" data and increase recording depth
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- Subsampling
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@ -55,6 +49,11 @@ external Rx/Tx pins to be ready to debug or control all your Wishbone peripheral
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- UART2Wishbone (provided by LiteScope)
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- Ethernet2Wishbone ("Etherbone") (when used with LiteEth)
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- PCIe2Wishbone (when used with LitePCIe)
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- Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...
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[> Proven
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----------
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LiteScope has already been used to investigate issues on commercial and open-source designs.
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[> Possible improvements
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-------------------------
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@ -62,7 +61,7 @@ external Rx/Tx pins to be ready to debug or control all your Wishbone peripheral
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- add protocols analyzers
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- add signals injection/generation
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- add storage in DRAM
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- add storage in HDD with LiteSATA core (to be released soon!)
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- add storage in HDD with LiteSATA core
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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@ -71,7 +70,7 @@ devel [AT] lists.m-labs.hk.
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[> Getting started
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------------------
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-------------------
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1. Install Python3 and your vendor's software
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2. Obtain Migen and install it:
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@ -83,16 +82,13 @@ devel [AT] lists.m-labs.hk.
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3. Obtain MiSoC:
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git clone https://github.com/m-labs/misoc --recursive
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4. Obtain LiteScope:
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git clone https://github.com/enjoy-digital/litescope
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5. Build and load test design:
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4. Build and load test design:
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go to example_designs/
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./make.py -p [your_platform] all load-bitstream
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Supported platforms are the ones already supported by Mibuild:
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de0nano, m1, mixxeo, kc705, zedboard...
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6. Test design:
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5. Test design:
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go to test and run:
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./make.py --port your_serial_port test_inout (will blink leds)
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./make.py --port your_serial_port test_logic_analyzer (will capture counter)
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@ -100,16 +96,18 @@ devel [AT] lists.m-labs.hk.
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tests can also be executed over Etherbone (provided with LiteEth):
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./make.py --ip_address fpga_ip_address your_test
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[> Simulations:
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XXX convert simulations
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[> Simulations
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---------------
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TODO
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[> Tests :
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XXX convert tests
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[> Tests
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---------
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TODO
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[> License
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-----------
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LiteScope is released under the very permissive two-clause BSD license. Under the
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terms of this license, you are authorized to use LiteScope for closed-source
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------------
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LiteScope is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteScope for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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